圖3.DS90UB913Q/DS90UB914Q典型應用框圖

The DS90UB913Q/914Q evaluation boards consist of two sections. The first part of the board provides the point-to-point interface for transmitting parallel video data. The second part of the board allows bi-directional control communication of an I2C bus control of using a MCU/FPGA to programming a remote peripheral device via the Serializer.

2012-8-22 12:20:20 上傳

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圖4.DS90UB913Q/914Q評估板外形圖

The DS90UB913Q/914Q chipset supports a variety of automotive mega-pixel camera systems over a two (2) wire serial stream. The single differential pair (FPD-Link III) is well-suited for direct connections between an imager and Host Controller/Electronic Control Unit (ECU)/FPGA. The bidirectional control channel of the DS90UB913Q/914Q provides seamless communication between the ECU/FPGA and the imager module. Transmission of a full-duplex high-speed video data (10/12 bits of parallel data, two SYNC bits and PCLK), with transparent bi-directional control channel (I2C) over the same serial video link. Additionally, there are four unidirectional general purpose (GPI and GPO) signal lines from the Deserializer to the Serializer. This interface allows transparent (no dependency of video blanking interval) ,full-duplex communication over a single high-speed differential pair. The Serializer and Deserializer communicate data at PCLK clocks speeds ranging from 10 to 100 MHz and I2C bus rates up to 400 kbps at up to 25 meters cable length over -40 to +105 Deg C.

DS90UB913Q/914Q評估板主要特性:

On-board Rosenberger connectors for use with Leoni-Dacar cables (not included)

Optional single ended coaxial connectors to work with coaxial cables

Supports a variety of automotive mega-pixel camera systems over a two (2) wire serial stream

Requires only a single 5V supply

Power transfer over coax or power transfer over differential pair capability

Enables high-speed video data transmission, with integrated low latency bi-directional control, over a single twisted pair cable

Delivers 10/12 bits of parallel data, two SYNC bits and PCLK, with a bidirectional I2C bus control channel

Four additional unidirectional general purpose (GPI and GPO) signal lines from the Deserializer to the Serializer

Full-duplex communication and asymmetrical bi-directional control over a single high-speed differential pair, without video blanking intervals

Transmit data at PCLK clocks speeds, ranging from 10 to 100 MHz

I2C bus rates up to 400 kbps

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圖5.DS90UB913Q EVK電路圖(1)

2012-8-22 12:20:17 上傳

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圖6.DS90UB913Q EVK電路圖(2)

2012-8-22 12:20:16 上傳

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圖7.DS90UB913Q EVK電路圖(3)

2012-8-22 12:20:14 上傳

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圖8.DS90UB914Q EVK電路圖(1)

2012-8-22 12:20:13 上傳

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