FPGA is widely popular in systems for its flexibility and adaptability. Increasingly, it is being used in high volume applications. As volumes grow, system designers can consider integration of the FPGA into an SoC to reduce cost, reduce power and/or improve performance.

FPGA以其強(qiáng)大的靈活性和適應(yīng)性見(jiàn)長(zhǎng)。系統(tǒng)設(shè)計(jì)師在設(shè)計(jì)大容量復(fù)雜應(yīng)用時(shí)，越來(lái)越多的考慮使用SoC中集成FPGA方案來(lái)減小功耗并提高性能。

There are two options for integrating FPGA into an SoC:o FPGA chiplets, which replace the power hungry SERDES/PHYs with special die-to-die interconnects to communicate with the companion SoC dieo eFPGA, which is an IP block that is put on the SoC dieHow do these alternatives compare? As we’ll see, it depends on the application and the priorities.
There are several applications where integrating an FPGA has advantages:1.In an existing system where an FPGA is paired with an SoC, for example a Smart NIC or Microsoft Azure2.To provide flexibility for an SoC to change algorithms and/or protocols as standards change or for the needs of different customers3.Acceleration for SoCs where critical workloads run faster on parallel FPGA than processors4.To provide programmable state machines in architectures that have arrays of compute elements, such as many new AI accelerators

將FPGA集成進(jìn)SoC的好處顯而易見(jiàn)：1.對(duì)于已有的FPGASoC系統(tǒng)，例如SmartNIC智能網(wǎng)卡方案或者微軟Azure云中，可以進(jìn)一步提高集成度和性能。2.讓原本不具備靈活性的SoC具備一定的可編程能力，讓終端用戶可以根據(jù)需求的變化修改協(xié)議和算法。3.給SoC提供一個(gè)加速核，把一些適合FPGA并行計(jì)算的工作負(fù)載offload到FPGA上進(jìn)行。4.在SoC架構(gòu)中提供可編程狀態(tài)機(jī)等計(jì)算單元，作為新型AI引擎總而言之一句話，F(xiàn)PGA具備的好處，SoC集成后可以全部繼承。

eFPGA（SoC）& cFPGA（SiP）
目前流行的兩種集成方案分別是embedded FPGA(以下簡(jiǎn)稱eFPGA集成方案)以及FPGA Chiplets(以下簡(jiǎn)稱cFPGA集成方案)1.eFPGA集成方案eFPGA是嵌入到SoC中的FPGA IP核，可以是軟核或者是硬核，工藝節(jié)點(diǎn)往往需要和SoC保持一致。

eFPGA的框架(來(lái)自QuickLogic)

eFPGA的概念(來(lái)自Achronix)

eFPGA通常具有比傳統(tǒng)FPGA更多的輸入和輸出，可連接到總線、數(shù)據(jù)路徑、控制路徑、PHY等部件中。這個(gè)技術(shù)多年前在學(xué)術(shù)界就已被提出，直到近5年才逐步被廣泛接受，美國(guó)、法國(guó)、中國(guó)也涌現(xiàn)了一系列專注于eFPGA的公司，并將其成功的商業(yè)化。cFPGA集成方案Chiplet的概念則最早來(lái)自 DARPA 的 CHIPS(Common Heterogeneous Integration and IP Reuse Strategies)項(xiàng)目。是通過(guò)die-to-die內(nèi)部互聯(lián)技術(shù)將多個(gè)模塊芯片與底層基礎(chǔ)芯片封裝在一起，構(gòu)成多功能的異構(gòu)System in Package（SiP）芯片的模式。理論上講，這種技術(shù)是一種短周期、低成本的集成第三方芯片（例如I/O、存儲(chǔ)芯片、NPU等）的技術(shù)，各個(gè)模塊芯片的工藝節(jié)點(diǎn)可以不同。Chiplet是業(yè)界為了彌補(bǔ)硅工藝技術(shù)增長(zhǎng)放緩所做的幾項(xiàng)努力之一。它們起源于多芯片模塊，誕生于20世紀(jì)70年代，迄今為止，已經(jīng)有很多公司早早地創(chuàng)建了自己的 Chiplet 生態(tài)系統(tǒng)，包括Marvell、AMD、Intel等。

Chiplet的框架

Chiplet的概念

The power-hungry high speed SERDES are the connectivity tiles in this diagram. EMIB is Intel’s proprietary wide-bus high bandwidth chip-to-chip interconnect.The FPGA chiplet in the middle is primarily digital logic. Intel and Xilinx will, for certain customers at least, provide die for integration into SoCs using interposers, see an example below:

Intel 片間互連技術(shù)方案(來(lái)自Intel)In this way, an SoC and an FPGA chiplet can be co-packaged with a wide, high speed bus connecting them.最新型的FPGA(無(wú)論是X家還是I家)，實(shí)際上都使用了Chiplet技術(shù)。Intel給自家的片間互連技術(shù)起了一個(gè)高大上的名字：“嵌入式多片互連橋接，Embedded Multi-die Interconnect Bridge”EMIB (如上圖所示)，其混合了SoC和SiP技術(shù)。Xilinx則從7系開(kāi)始就采用了片間互連技術(shù)來(lái)在有限的面積下通過(guò)堆疊實(shí)現(xiàn)超大邏輯容量、Serdes高速接口以及HBM高帶寬存儲(chǔ)的融合。

Xilinx 片間互連技術(shù)歷史（來(lái)自Xilinx）

Pros and cons of cFPGA vs eFPGA

兩種方案的優(yōu)劣對(duì)比(由于原文作者是FlexLogix的CEO，因此文章也傾向性地強(qiáng)調(diào)了eFPGA的好處)

The disadvantages of the chiplet approach are:othe high cost of multi-die packaging using substrateso the need to use a specialized die-to-die interface on your SoC that you may not be familiar with or are unable to get from your PHY IP suppliero the smallest FPGA chiplets available still have a large number of LUTs which may exceed the requirementThe applications where eFPGA may be a better solution are:o those where the die cost of eFPGA+SoC is lower than the cost of the interposer and chiplet+SoCo those where the amount of eFPGA required is 10s of thousands of LUTs: such small chiplets are not available and the die area required on the SoC is minimalo architectures where eFPGA is distributed across the die in many locations, such as in an array of compute elements where the eFPGA is a programmable state machine for local control of high speed compute blocks: chiplets are really only practical for a single large block of FPGA

cFPGASiP方案的優(yōu)勢(shì)：

1.支持多工藝節(jié)點(diǎn)的片間融合。

2.旨在打造標(biāo)準(zhǔn)化、模塊化的IP，因此FPGA部分通常是一個(gè)固定芯片模塊，SiP設(shè)計(jì)的重構(gòu)迭代速度更快。

eFPGASoC方案的優(yōu)勢(shì)：

1.無(wú)需去了解你可能并不熟悉的SoC片間互連技術(shù)(有時(shí)無(wú)法從你的PHY IP提供商那獲得)。

2.免去了高昂的多片封裝基板費(fèi)用。

3.旨在強(qiáng)化FPGA的可定制性，在個(gè)性化細(xì)節(jié)定制方面更加靈活。

編輯：hfy