在SpinalHDL中使用之前已有的Verilog等代碼的時(shí)候需要將這些代碼包在一個(gè)BlackBox里面，但是如果這些代碼里面有時(shí)鐘和復(fù)位，我們需要怎么將時(shí)鐘和復(fù)位端口和SpinalHDL中已有的時(shí)鐘域連接起來呢？

當(dāng)BlackBox中只有一個(gè)時(shí)鐘的時(shí)候可以直接使用mapClockDomain完成時(shí)鐘信號(hào)和復(fù)位信號(hào)的賦值。在mapClockDomain中如果沒有指定時(shí)鐘域的話就采用的是默認(rèn)時(shí)鐘域。

import spinal.core._
import spinal.lib._
class BK extends BlackBox{
    val clka = in Bool()
    val rsta = in Bool()
    val din = in Bool()
    val dout = out Bool()
    mapClockDomain(clock = clka, reset = rsta)
}
class TestBlackBox extends Component {
    val din = in Bool()
    val dout = out Bool()
    val bk = new BK
    bk.din <> din
    bk.dout <> dout
}
object TestBlackBox extends App{
    SpinalVerilog(new TestBlackBox)
}

當(dāng)有兩個(gè)時(shí)鐘域的時(shí)候，就需要把時(shí)鐘域給指定一下了，在下面代碼中將時(shí)鐘域通過參數(shù)的方式傳了進(jìn)來。

import spinal.core._
import spinal.lib._
class BK(clockDomaina: ClockDomain, clockDomainb: ClockDomain) extends BlackBox{
    val clka = in Bool()
    val rsta = in Bool()
    val clkb = in Bool()
    val rstb = in Bool()
    val din = in Bool()
    val dout = out Bool()
    mapClockDomain(clockDomaina,clock = clka, reset = rsta)
    mapClockDomain(clockDomainb,clock = clkb, reset = rstb)
}
class TestBlackBox extends Component {
    val din = in Bool()
    val dout = out Bool()
    val clkb = in Bool()
    val resetb = in Bool()
    val clockDomainb = ClockDomain(clock = clkb,reset = resetb)
    val bk = new BK(this.clockDomain,clockDomainb)//默認(rèn)時(shí)鐘域和新建的時(shí)鐘域b
    bk.din <> din
    bk.dout <> dout
}
object TestBlackBox extends App{
    SpinalVerilog(new TestBlackBox)
}

因?yàn)樵赟pinalHDL中默認(rèn)時(shí)鐘域是高復(fù)位的，但是我們已有的IP可能是低復(fù)位的，這個(gè)時(shí)候就需要在mapClockDomain中指定一下復(fù)位信號(hào)是HIGH還是LOW。在下面代碼中就將時(shí)鐘域b下面的復(fù)位指定為低復(fù)位。

import spinal.core._
import spinal.lib._
class BK(clockDomaina: ClockDomain, clockDomainb: ClockDomain) extends BlackBox{
    val clka = in Bool()
    val rsta = in Bool()
    val clkb = in Bool()
    val rstb = in Bool()
    val din = in Bool()
    val dout = out Bool()
    mapClockDomain(clockDomaina,clock = clka, reset = rsta)
    mapClockDomain(clockDomainb,clock = clkb, reset = rstb, resetActiveLevel = LOW)
}
class TestBlackBox extends Component {
    val din = in Bool()
    val dout = out Bool()
    val clkb = in Bool()
    val resetb = in Bool()
    val clockDomainb = ClockDomain(clock = clkb,reset = resetb)
    val bk = new BK(this.clockDomain,clockDomainb)
    bk.din <> din
    bk.dout <> dout
}
object TestBlackBox extends App{
    SpinalVerilog(new TestBlackBox)
}

以上三種情況應(yīng)該足夠應(yīng)對(duì)一般情況下BlackBox的時(shí)鐘域的賦值了。

審核編輯：湯梓紅