1.eFlexPWM 介紹

2.PWM GPIO 口配置

3.eFlexPWM 配置（PWM 配置）

4.eFlexPWM 配置（死區 配置）

5.eFlexPWM 配置代碼

6.開發板測試與波形

7.參考文檔

1. eFlexPWM 介紹

eFlexPWM 是 LPC553X 的一個高級 Timer 外設，針對電機應用和電源應用做了優化，并能夠產生各種不同的 PWM 類型，PWM 輸出功能主要有中心對齊（Center Aligned）、邊緣對齊（Edge Aligned）、相移（Phase Shifted）、雙開關（Double Switching）功能。

增強的輸入捕獲功能（Enhanced Capture），可以精確測量 PWM 頻率和占空比。

一個 eFlexPWM 中還有 4 個子模塊，4 個子模塊之間具有同步開關功能，事件產生時同時動作，消除了中斷和軟件操作上的延時，特別適合于電機的換相操作。

eFlexPWM 還可以在精確的時刻觸發 ADC 進行采樣，在電機相電流采樣中特別方便。

此外還有 counter 不同的重載邏輯，多樣的寄存器 Buffer 更新時機，PWM 互補和死區自動生成等功能，本文主要講解如何生成 6 路互補帶死區的 PWM 以應用于電機控制，這些 PWM 通過 PreDriver 后驅動 MOS 或 IGBT，下圖是 eFlexPWM 框圖。

2. PWM GPIO 口配置

GPIO 口的初始化和分配使用 MCUXpresso config Tools 來配置，可以減少錯誤和沖突，配置完后將自動生成的 pin_mux.c 和 pin_mux.h 拷貝到工程中并在 main 中執行 BOARD_InitBootPins() 函數即可，圖中的 A,0 和 B,0 為互補到死區的一對 PWM，將分別接到 Predriver 后驅動圖中 MOS 管的 T1 和 T2 信號，其他依次類推。

3. eFlexPWM 配置（頻率配置）

PWM 頻率的配置主要通過配置 eFlexPWM 的 INIT 和 VAL1 寄存器配置，counter 從 INIT 開始計數，計到 VAL1 時重新計數，如果要產生 20KHz 的 PWM，計算過程為：INIT = 定時器時鐘/20KHz/2 = 150MHz/20KHz/2 = 3750，VAL1 =定時器時鐘/20KHz/2 -1 = 3749。部分代碼：

/* value register initial values, duty cycle 50% */

PWMBase->SM[0].INIT = PWM_INIT_INIT((uint16_t)(-(M1_PWM_MODULO / 2)));//1875

PWMBase->SM[1].INIT = PWM_INIT_INIT((uint16_t)(-(M1_PWM_MODULO / 2)));

PWMBase->SM[2].INIT = PWM_INIT_INIT((uint16_t)(-(M1_PWM_MODULO / 2)));

PWMBase->SM[3].INIT = PWM_INIT_INIT((uint16_t)(-(M1_PWM_MODULO / 2)));

PWMBase->SM[0].VAL1 = PWM_VAL1_VAL1((uint16_t)((M1_PWM_MODULO / 2) - 1));

PWMBase->SM[1].VAL1 = PWM_VAL1_VAL1((uint16_t)((M1_PWM_MODULO / 2) - 1));

PWMBase->SM[2].VAL1 = PWM_VAL1_VAL1((uint16_t)((M1_PWM_MODULO / 2) - 1));

PWMBase->SM[3].VAL1 = PWM_VAL1_VAL1((uint16_t)((M1_PWM_MODULO / 2) - 1));

4. eFlexPWM 配置（死區配置）

為了防止上下橋同時開通造成短路，可以根據 MOS 或 IGBT 的開關速度設置合適的死區時間，通過 DTCNT0 寄存器設置，計算方式如下， M1_PWM_DEADTIME 單位為 us，其位置為上圖中的藍色部分，部分代碼：

PWMBase->SM[0].DTCNT0 = ((M1_PWM_DEADTIME * (MCU_CLOCK_FREQ / 1000000U)) / 1000U);

5. eFlexPWM 配置代碼

eFlexPWM 的配置主要是開啟時鐘、復位、設置 INIT、VAL1 確定頻率、死區、模式、占空比設置寄存器 VAL2、VAL3，以下代碼為基于寄存器方式的完整配置代碼：

void eFlexPWM0_init(void)

{

PWM_Type *PWMBase = (PWM_Type *)PWM0;

/*eFlexPWM0 init*/

SYSCON->PWM0SUBCTL = (SYSCON_PWM0SUBCTL_CLK0_EN_MASK | SYSCON_PWM0SUBCTL_CLK1_EN_MASK | SYSCON_PWM0SUBCTL_CLK2_EN_MASK | SYSCON_PWM0SUBCTL_CLK3_EN_MASK); //Enable Sub-module0 clock

CLOCK_EnableClock(kCLOCK_Pwm0);

/* value register initial values, duty cycle 50% */

PWMBase->SM[0].INIT = PWM_INIT_INIT((uint16_t)(-(M1_PWM_MODULO / 2)));//1875

PWMBase->SM[1].INIT = PWM_INIT_INIT((uint16_t)(-(M1_PWM_MODULO / 2)));

PWMBase->SM[2].INIT = PWM_INIT_INIT((uint16_t)(-(M1_PWM_MODULO / 2)));

PWMBase->SM[3].INIT = PWM_INIT_INIT((uint16_t)(-(M1_PWM_MODULO / 2)));

PWMBase->SM[0].VAL1 = PWM_VAL1_VAL1((uint16_t)((M1_PWM_MODULO / 2) - 1));

PWMBase->SM[1].VAL1 = PWM_VAL1_VAL1((uint16_t)((M1_PWM_MODULO / 2) - 1));

PWMBase->SM[2].VAL1 = PWM_VAL1_VAL1((uint16_t)((M1_PWM_MODULO / 2) - 1));

PWMBase->SM[3].VAL1 = PWM_VAL1_VAL1((uint16_t)((M1_PWM_MODULO / 2) - 1));

// TODO - TEST, init to 0 otherwise (see above).

PWMBase->SM[0].VAL2 = (uint16_t)(-(M1_PWM_MODULO/4));

PWMBase->SM[1].VAL2 = (uint16_t)(-(M1_PWM_MODULO/4));

PWMBase->SM[2].VAL2 = (uint16_t)(-(M1_PWM_MODULO/4));

PWMBase->SM[3].VAL2 = (uint16_t)(-(M1_PWM_MODULO/4));

PWMBase->SM[0].VAL3 = (uint16_t)((M1_PWM_MODULO/4));

PWMBase->SM[1].VAL3 = (uint16_t)((M1_PWM_MODULO/4));

PWMBase->SM[2].VAL3 = (uint16_t)((M1_PWM_MODULO/4));

PWMBase->SM[3].VAL3 = (uint16_t)((M1_PWM_MODULO/4));

/* PWM0 module 0 trigger on VAL4 enabled for ADC synchronization */

PWMBase->SM[0].VAL4 = PWM_VAL4_VAL4((uint16_t)((-(M1_PWM_MODULO / 2))));

/*xx_xxx1b - PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value */

PWMBase->SM[0].TCTRL |= PWM_TCTRL_OUT_TRIG_EN(0b010001);//PWAOT0 PWBOT1 TRGFRQ OUT_TRIG_EN

PWMBase->SM[0].INTEN = (0x1UL << 12UL);//RIE,Reload Interrupt Enable?

/* set deadtime (number of Fast Peripheral Clocks)

DTCNT0,1 = T_dead * f_fpc = 1.0us * 150MHz = 150 */

PWMBase->SM[0].DTCNT0 = ((M1_PWM_DEADTIME * (MCU_CLOCK_FREQ / 1000000U)) / 1000U);

PWMBase->SM[1].DTCNT0 = ((M1_PWM_DEADTIME * (MCU_CLOCK_FREQ / 1000000U)) / 1000U);

PWMBase->SM[2].DTCNT0 = ((M1_PWM_DEADTIME * (MCU_CLOCK_FREQ / 1000000U)) / 1000U);

PWMBase->SM[3].DTCNT0 = ((M1_PWM_DEADTIME * (MCU_CLOCK_FREQ / 1000000U)) / 1000U);

PWMBase->SM[0].DTCNT1 = ((M1_PWM_DEADTIME * (MCU_CLOCK_FREQ / 1000000U)) / 1000U);

PWMBase->SM[1].DTCNT1 = ((M1_PWM_DEADTIME * (MCU_CLOCK_FREQ / 1000000U)) / 1000U);

PWMBase->SM[2].DTCNT1 = ((M1_PWM_DEADTIME * (MCU_CLOCK_FREQ / 1000000U)) / 1000U);

PWMBase->SM[3].DTCNT1 = ((M1_PWM_DEADTIME * (MCU_CLOCK_FREQ / 1000000U)) / 1000U);

/* Control Register */

PWMBase->SM[0].CTRL = ( 0x0UL << 12UL )? //LDFQ

|( 0x0UL << 11UL )? //HALF

|( 0x1UL << 10UL )? //FULL

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

/* Control Register */

PWMBase->SM[1].CTRL = ( 0x0UL << 12UL )? //LDFQ

|( 0x0UL << 11UL )? //HALF

|( 0x1UL << 10UL )? //FULL

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

/* Control Register */

PWMBase->SM[2].CTRL = ( 0x0UL << 12UL )? //LDFQ

|( 0x0UL << 11UL )? //HALF

|( 0x1UL << 10UL )? //FULL

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

/* Control Register */

PWMBase->SM[3].CTRL = ( 0x0UL << 12UL )? //LDFQ

|( 0x0UL << 11UL )? //HALF

|( 0x1UL << 10UL )? //FULL

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

|( 0x0UL <

|( 0x0UL << 0UL ); //DBLEN

/* Fault0 trigger, Disable X,Disable B,Disable A */

// PWMBase->SM[0].DISMAP[0] = 0xF111U;

// PWMBase->SM[1].DISMAP[0] = 0xF111U;

// PWMBase->SM[2].DISMAP[0] = 0xF111U;

// PWMBase->SM[3].DISMAP[0] = 0xF111U;

PWMBase->SM[0].DISMAP[0] = 0;

PWMBase->SM[1].DISMAP[0] = 0;

PWMBase->SM[2].DISMAP[0] = 0;

PWMBase->SM[3].DISMAP[0] = 0;

/* PWMs are re-enabled at PWM full cycle / half cycle */

PWMBase->FSTS = (PWMBase->FSTS & ~(PWM_FSTS_FFULL_MASK | PWM_FSTS_FHALF_MASK)) | PWM_FSTS_FFULL(0x1) | PWM_FSTS_FHALF(0x1);

/* PWM fault filter - 3 Fast periph. clocks sample rate, 5 agreeing samples to activate */

PWMBase->FFILT = (PWMBase->FFILT & ~PWM_FFILT_FILT_PER_MASK) | PWM_FFILT_FILT_PER(2);

/* All interrupts disabled, safe manual fault clearing, inversed logic (trigger level = high) */

PWMBase->FCTRL &= ~(PWM_FCTRL_FLVL_MASK | PWM_FCTRL_FAUTO_MASK | PWM_FCTRL_FSAFE_MASK | PWM_FCTRL_FIE_MASK); /* clear FCTRL register prior further settings */

PWMBase->FCTRL |= PWM_FCTRL_FLVL(0x1U);

PWMBase->FCTRL |= PWM_FCTRL_FAUTO(0x1U);

PWMBase->FCTRL |= PWM_FCTRL_FSAFE(0x1U);

PWMBase->FCTRL |= PWM_FCTRL_FIE(0U); /* FAULT 0 & FAULT 1 - Interrupt disable */

/* Clear all fault flags */

PWMBase->FSTS = (PWMBase->FSTS & ~PWM_FSTS_FFLAG_MASK) | PWM_FSTS_FFLAG(0xF);

PWMBase->MASK = 0;//UPDATE_MASK MASKA MASKB MASKx

PWMBase->SWCOUT = 0;

PWMBase->DTSRCSEL = 0;//

PWMBase->SM[0].FRCTRL |= ((0UL << 4UL) | (0UL << 2UL) | (0UL << 1UL)) ;//FRAC45_EN 4,FRAC23_EN 2,FRAC1_EN1

PWMBase->SM[0].FRACVAL2 = 0 << 11UL;

PWMBase->SM[0].FRACVAL3 = 0 << 11UL;

PWMBase->SM[1].FRACVAL2 = 0 << 11UL;

PWMBase->SM[1].FRACVAL3 = 0 << 11UL;

PWMBase->SM[2].FRACVAL2 = 0 << 11UL;

PWMBase->SM[2].FRACVAL3 = 0 << 11UL;

PWMBase->SM[3].FRACVAL2 = 0 << 11UL;

PWMBase->SM[3].FRACVAL3 = 0 << 11UL;

PWMBase->SM[0].CTRL2 = ( 0x0UL << 15UL ) //DBGEN

|( 0x0UL << 14UL ) //WAITEN,Sleep Enable

|( 0x0UL << 13UL ) //INDEP,0b - PWM_A and PWM_B form a complementary PWM pair.

|( 0x0UL << 12UL ) //PWM23_INIT,

|( 0x0UL << 11UL ) //PWM45_INIT

|( 0x0UL << 10UL ) //PWMX_INIT

|( 0x0UL << 8UL ) //INIT_SEL,counter load init value,Local sync,Master reload,Master sync,EXT_SYNC

|( 0x0UL << 7UL ) //FRCEN

|( 0x0UL << 6UL ) //FORCE

|( 0x0UL << 3UL ) //FORCE_SEL,local force，master force，local reload，master reload，local sync，master sync，external force，external sync

|( 0x0UL << 2UL ) //RELOAD_SEL,0b - The local RELOAD signal

|( 0x0UL << 0UL ); //CLK_SEL,

//00b - The IPBus clock

//01b - EXT_CLK

//10b - Submodule 0’s clock (AUX_CLK)

PWMBase->SM[1].CTRL2 = ( 0x0UL << 15UL ) //DBGEN

|( 0x0UL << 14UL ) //WAITEN,Sleep Enable

|( 0x0UL << 13UL ) //INDEP,0b - PWM_A and PWM_B form a complementary PWM pair.

|( 0x0UL << 12UL ) //PWM23_INIT,

|( 0x0UL << 11UL ) //PWM45_INIT

|( 0x0UL << 10UL ) //PWMX_INIT

|( 0x2UL << 8UL ) //INIT_SEL,counter load init value,Local sync,Master reload,Master sync,EXT_SYNC

|( 0x0UL << 7UL ) //FRCEN

|( 0x0UL << 6UL ) //FORCE

|( 0x1UL << 3UL ) //FORCE_SEL,local force，master force，local reload，master reload，local sync，master sync，external force，external sync

|( 0x1UL << 2UL ) //RELOAD_SEL,1b - The master RELOAD signal

|( 0x0UL << 0UL ); //CLK_SEL,

//00b - The IPBus clock

//01b - EXT_CLK

//10b - Submodule 0’s clock (AUX_CLK)

PWMBase->SM[2].CTRL2 = ( 0x0UL << 15UL ) //DBGEN

|( 0x0UL << 14UL ) //WAITEN,Sleep Enable

|( 0x0UL << 13UL ) //INDEP,0b - PWM_A and PWM_B form a complementary PWM pair.

|( 0x0UL << 12UL ) //PWM23_INIT,

|( 0x0UL << 11UL ) //PWM45_INIT

|( 0x0UL << 10UL ) //PWMX_INIT

|( 0x2UL << 8UL ) //INIT_SEL,counter load init value,Local sync,Master reload,Master sync,EXT_SYNC

|( 0x0UL << 7UL ) //FRCEN

|( 0x0UL << 6UL ) //FORCE

|( 0x1UL << 3UL ) //FORCE_SEL,local force，master force，local reload，master reload，local sync，master sync，external force，external sync

|( 0x1UL << 2UL ) //RELOAD_SEL,1b - The master RELOAD signal

|( 0x0UL << 0UL ); //CLK_SEL,

//00b - The IPBus clock

//01b - EXT_CLK

//10b - Submodule 0’s clock (AUX_CLK)

PWMBase->SM[3].CTRL2 = ( 0x0UL << 15UL ) //DBGEN

|( 0x0UL << 14UL ) //WAITEN,Sleep Enable

|( 0x0UL << 13UL ) //INDEP,0b - PWM_A and PWM_B form a complementary PWM pair.

|( 0x0UL << 12UL ) //PWM23_INIT,

|( 0x0UL << 11UL ) //PWM45_INIT

|( 0x0UL << 10UL ) //PWMX_INIT

|( 0x2UL << 8UL ) //INIT_SEL,counter load init value,Local sync,Master reload,Master sync,EXT_SYNC

|( 0x0UL << 7UL ) //FRCEN

|( 0x0UL << 6UL ) //FORCE

|( 0x1UL << 3UL ) //FORCE_SEL,local force，master force，local reload，master reload，local sync，master sync，external force，external sync

|( 0x1UL << 2UL ) //RELOAD_SEL,1b - The master RELOAD signal

|( 0x0UL << 0UL ); //CLK_SEL,

//00b - The IPBus clock

//01b - EXT_CLK

//10b - Submodule 0’s clock (AUX_CLK)

/* Start PWMs (set load OK flags and run - we need to trigger the ADC) */

PWMBase->MCTRL = (PWMBase->MCTRL & ~PWM_MCTRL_CLDOK_MASK) | PWM_MCTRL_CLDOK(0xF);

PWMBase->MCTRL = (PWMBase->MCTRL & ~PWM_MCTRL_LDOK_MASK) | PWM_MCTRL_LDOK(0xF);

PWMBase->MCTRL = (PWMBase->MCTRL & ~PWM_MCTRL_RUN_MASK) | PWM_MCTRL_RUN(0xF);

//PWMBase->OUTEN = 0xFF0;//0xFF0,11-8,PWMA3_EN ~ PWMA0_EN, 7-4 PWMB3_EN ~ PWMB0_EN, 3-0 PWMX3_EN ~ PWMX0_EN

/* Enable & setup interrupt from PWMA */

NVIC_SetPriority(FLEXPWM0_RELOAD0_IRQn, 0U);

NVIC_EnableIRQ(FLEXPWM0_RELOAD0_IRQn);

}

6. 開發板測試與波形

本文使用 NXP 原廠的 LPC55S36-EVK 測試，生成的 6 路 PWM 對應原理圖中的 PWM_AT、PWM_AB、 PWM_BT、PWM_BB、 PWM_CT、PWM_CB，如下圖所示：

示波器探頭連接開發板 J10 插件 15 與 13 腳，如下圖中紅框部分如圖所示：

示波器黃色探頭為 PWM_AT，藍色為 PWM_AB，測量為 40KHz PWM，死區 1us，與設置的一致。