文檔要點
框圖
首先，UG1085 Figure 30‐1: Block Diagram of the Controller for PCIe 提供了MPSoC PCIe部分的框圖。從中可以看到，客戶需要的是Ingress傳輸，即X86的PCIe請求達到MPSoC PCIe 控制器后，轉換成AXI Master，再取讀寫MPSoC的DDR內存。

地址轉換窗口
UG1085中的“Address Translation”部分，說明了MPSoC PCIe 控制器提供了8個地址轉換的窗口。

Address Translation

The bridge provides eight fully-configurable address apertures to support address
translation both for ingress (from PCIe to AXI) and egress (from AXI to PCIe) transactions.
? In an AXI master, up to eight ingress translation regions can be set up. Translation is
done for the PCIe TLPs that are not decoded as MSI or MSI-X interrupts or internal
DMA transactions.

地址轉換
如果PCIe地址的高位（基地址），等于source address (tran_src_base) 的高位，就會進行PCIe地址轉換。

In the following discussions, the term tran refers to ingress/egress translation. For example,
tran_size refers to translation size and a tran_src_base refers to ingress/egress_src_base.

A translation is hit when the following occurs.
? Translation is enabled (tran_enable == 1).
? The tran_src_base[63:(12+tran_size)] == source address [63:(12+tran_size)].

轉換后的目標地址，等于destination address (tran_dst_base)的高位（基地址），加上PCIe地址的低位（偏移地址）。

On a hit, the upper source address bits are replaced with destination base address bits
before forwarding the transaction to the destination.
Destination address = {tran_dst_base[63:(12+tran_size)] source address[12+tran_size]}.

地址轉換窗口示例

1. Consider host assigns PCIe BAR2 = 0xFFA0_0000 ; 1MB size.
2. Ingress source base = 0xFFA0_0000 ; destination base = 0x44A0_0000 ;
aperture size = 64 KB
3. Incoming PCIe memory transaction hitting BAR2 at 0xFFA0_xyzw translates to address
0x44A0_xyzw on AXI master port.

示例代碼
AMD提供了Standalone的示例"xilinxprocessoriplibdriverspciepsuexamplesXpciepsu_ep_enable_example.c” 和 “xilinxprocessoriplibdriverspciepsusrcXpciepsu_ep.c”。

總體流程
"xilinxprocessoriplibdriverspciepsuexamplesXpciepsu_ep_enable_example.c” 中的main()實現了總體流程，包括檢查PCIe 鏈路狀態，PCIe配置狀態，最后再配置地址轉換窗口。

int main()
{
int Status = XST_SUCCESS;
#ifdef XPAR_PSU_PCIE_DEVICE_ID
XPciePsu_InitEndPoint(&PciePsuInstance, XPAR_PSU_PCIE_DEVICE_ID);

xil_printf("Waiting for PCIe Link uprn");
XPciePsu_EP_WaitForLinkup(&PciePsuInstance);
xil_printf("PCIe Link up...rn");

XPciePsu_EP_BridgeInitialize(&PciePsuInstance);
xil_printf("Bridge Init done...rn");

XPciePsu_EP_WaitForEnumeration(&PciePsuInstance);

xil_printf("Host driver indicated readyrn");
int result = XPciePsu_EP_SetupIngress(&PciePsuInstance,
INGRESS_NUM, BAR_NUM, PS_DDR_ADDR);
if (result == XST_FAILURE) {
xil_printf("PCIE ingress setup failedrn");
} else {
xil_printf("PCIE Ingress Test donern");
}

#endif
return Status;
}

下面的參數定義了地址轉換窗口數量、PCIe BAR、MPSoC的DDR內存的基地址。可以根據需要修改。

BAR_NUM定義了PCIe BAR的序號，在PCIe Host上一定要使用對應的BAR中的地址來訪問。

#define INGRESS_NUM 0x0 /* Ingress num to setup ingress */
#define BAR_NUM 0x2 /* Bar no to setup ingress */
#define PS_DDR_ADDR 0x1000000 /* 32 or 64 bit PS DDR Addr

地址轉換配置代碼
XPciePsu_EP_SetupIngress()從PCIe BAR中讀到PCIe的基地址，寫入INGRESS0_SRC_BASE（tran_src_base， TRAN_INGRESS_SRC_BASE）。

接下來，XPciePsu_EP_SetupIngress()把MPSoC的DDR內存的基地址寫入INGRESS0_DST_BASE（tran_dst_base， TRAN_INGRESS_DST_BASE）。

最后，XPciePsu_EP_SetupIngress() 設置 INGRESS0_CONTROL（TRAN_INGRESS_CONTROL）的大小和使能位，使能地址轉換。

在這之后，PCIe Host就能讀寫MPSoC的在地址范圍[PS_DDR_ADDR, PS_DDR_ADDR+INGRESS_SIZE_ENCODING]內的DDR內存。

int XPciePsu_EP_SetupIngress(XPciePsu *PciePsuPtr, u32 IngressNum, u32 BarNum,
u64 Dst){
Xil_AssertNonvoid(PciePsuPtr != NULL);
u32 SrcLo;
u32 SrcHi;
u32 Val;
u32 DestLo;
u32 DestHi;
if (IngressNum > 7) {
return XST_FAILURE;
}

XPciePSU_ReadBar(PciePsuPtr, BarNum, &SrcLo, &SrcHi);

/*
* Using Ingress Address Translation 0 to setup translation
* to PS DDR
*/
XPciePsu_WriteReg(PciePsuPtr->Config.BrigReg,
(INGRESS0_SRC_BASE_LO + (IngressNum * INGRESS_SIZE)),
SrcLo & ~0xf);
XPciePsu_WriteReg(PciePsuPtr->Config.BrigReg,
(INGRESS0_SRC_BASE_HI +
(IngressNum * INGRESS_SIZE)), SrcHi);

XPciePsu_Dbg("Done writing the Ingress Src registersrn");

DestLo = XPCIEPSU_LOWER32BITS(Dst);
DestHi = XPCIEPSU_UPPER32BITS(Dst);
XPciePsu_WriteReg(PciePsuPtr->Config.BrigReg,
(INGRESS0_DST_BASE_LO +
(IngressNum * INGRESS_SIZE)), DestLo);
XPciePsu_WriteReg(PciePsuPtr->Config.BrigReg,
(INGRESS0_DST_BASE_HI +
(IngressNum * INGRESS_SIZE)), DestHi);

XPciePsu_Dbg("Done writing the Ingress Dst registersrn");

Val = XPciePsu_ReadReg(PciePsuPtr->Config.BrigReg, INGRESS0_CONTROL);

XPciePsu_Dbg("Read Ingress Control registerrn");

Val &= (u32)(~INGRESS_SIZE_MASK);
Val |= (((u32)INGRESS_SIZE_ENCODING (u32)INGRESS_ENABLE | (u32)INGRESS_SECURITY_ENABLE);
Val |= INGRESS_RD_WR_ATTR;
XPciePsu_WriteReg(PciePsuPtr->Config.BrigReg,
(INGRESS0_CONTROL + (IngressNum * INGRESS_SIZE)), Val);

XPciePsu_Dbg("Done setting up the ingress trasnslation registersrn");
return XST_SUCCESS;
}

注意事項
在PCIe Host和A53通過共享DDR內存的方式交互數據時，要注意cache管理。

對于A53寫、PCIe Host讀的數據，A53要做cache Flush操作，PCIe Host要做cache Invalidate操作。

對于PCIe Host寫、A53讀的數據，PCIe Host要做cache Flush操作，A53要做cache Invalidate操作。

另外，在UG1085、UG1087里，同一個寄存器的名稱，可能有出入。比如UG1085里的tran_dst_base，對應UG1087的TRAN_INGRESS_SRC_BASE_LO和TRAN_INGRESS_SRC_BASE_HI。

審核編輯：湯梓紅