An amplitude-stabilized sine-wave oscillator is shown in Figure 26. This circuit provides high purity sine-wave output down to low frequencies with minimum circuit complexity. An important advantage of this circuit is that the traditional tungsten filament lamp amplitude regulator is eliminated along with its time constant and linearity problems.
In addition, the reliability problems associated with a lamp are eliminated.
The Wien Bridge oscillator is widely used and takes advantage of the fact that the phase of the voltage across the parallel branch of a series and a parallel RC network connected in series, is the same as the phase of the applied voltage across the two networks at one particular frequency and that the phase lags with increasing frequency and leads with decreasing frequency. When this network—the Wien Bridge—is used as a positive feedback element around an amplifier, oscillation occurs at the frequency at which the phase shift is zero. Additional negative feedback is provided to set loop gain to unity at the oscillation frequency, to stabilize the frequency of oscillation, and to reduce harmonic distortion.
The circuit presented here differs from the classic usage only in the form of the negative feedback stabilization scheme. Circuit operation is as follows: negative peaks in excess of -8.25V cause D1 and D2 to conduct, charging C4. The charge stored in C4 provides bias to Q1, which determines amplifier gain. C3 is a low frequency roll-off capacitor in the feedback network and prevents offset voltage and offset current errors from being multiplied by amplifier gain.
Distortion is determined by amplifier open-loop gain and by the response time of the negative feedback loop filter, R5 and C4. A trade-off is necessary in determining amplitude stabilization time constant and oscillator distortion. R4 is chosen to adjust the negative feedback loop so that the FET is operated at a small negative gate bias. The circuit shown provides optimum values for a general purpose oscillator.

圖26給出了一個帶穩(wěn)幅功能的正弦波振蕩器。這個電路以最簡潔的結(jié)構(gòu)實現(xiàn)了高純凈度正弦波輸出，而且在較低的頻率上也是如此。這個電路的主要優(yōu)點之一是克服了傳統(tǒng)鎢絲燈幅值調(diào)節(jié)電路所帶來的時間常數(shù)以及線性度方面的問題。
此外，燈泡的可靠性問題也無需再考慮了。
文氏橋振蕩器一直都被廣泛地應(yīng)用著，該電路的原理是——如果將一個串聯(lián)RC網(wǎng)絡(luò)和一個并聯(lián)RC網(wǎng)絡(luò)串接起來，那么在某個特定頻率下，電路輸出電壓的相位將與輸入電壓的相位相等，而當(dāng)頻率升高時，輸出電壓相位滯后，當(dāng)頻率降低時，輸出電壓相位超前。這個電路就是“文氏橋”，如果以文氏橋作為放大器的正反饋路徑，那么當(dāng)相移等于0的時候，就會出現(xiàn)振蕩。為了使振蕩頻率穩(wěn)定并降低諧波失真，需要加入一個在震蕩頻率處能夠提供單位增益的負反饋路徑。
本電路與經(jīng)典電路的唯一區(qū)別在于負反饋穩(wěn)定部分。電路原理如下：超出-8.25V的負電平使D1和D2導(dǎo)通，給C4充電，C4儲存的電荷為Q1提供偏置，從而控制放大器的增益。C3在反饋電路中起低通濾波的作用，防止失調(diào)電壓和失調(diào)電流引起的誤差被放大到輸出端。
失真是開環(huán)增益和負反饋路徑中濾波器的時間常數(shù)R5C4造成的。設(shè)計者需要在穩(wěn)幅時間常數(shù)和振蕩器的失真度之間進行權(quán)衡。R4用來調(diào)整負反饋路徑，使FET工作在微小的門極反相偏置電壓下。對于一般性應(yīng)用，圖26電路中的參數(shù)可以提供最佳性能。