電子發燒友App
/*Store all of the data sampled in appropriate global variables*/
105. _adcc_SubmitBuffer(hADCCTimer0, SampleBuffer0, FRAME_INC0, FRAMES_IN_BUFFER); /*Return the buffer to the ADCC for use in the next events*/
106. break;
107. case ADI_ADCC_EVENT_BUFFER_PROCESSED:
108. break;
109. default:
110. break;
111. }
112. static void AdccTmr1Callback(void *pCBParam, uint32_t Event, void *pArg){
113. switch(Event){
114. case ADI_ADCC_EVENT_FRAME_PROCESSED:
115. Iv_adc = SampleBuffer1[IV_ADC];
116. Iw_adc = SampleBuffer1[IW_ADC];
117. MotorControl(); /*Run the current control algorithm*/
118.
119.
120. break;
121. case ADI_ADCC_EVENT_BUFFER_PROCESSED:
122. adi_adcc_SubmitBuffer(hADCCTimer1, SampleBuffer1,
FRAME_INC1, FRAMES_IN_BUFFER);
123. break;
124. default:
125. break;
126. }
127. return;
}
P17
/*************************************************
Enhanced Precision Timing Code
*************************************************/
/*Setup TRU for ADCC enhanced timing precision. Slave is ADCC0 trig 1 and master is GP timer 7
Added to SetpTRU() function in place of line 95 */
128. result = adi_tru_TriggerRoute(hTru, TRGS_ADCC0_TRIG0, TRGM_TIMER0_TMR7); // TRU device, slave, master
129. result = adi_tru_TriggerRoute(hTru, TRGS_TIMER0_TMR7, TRGM_PWM0_SYNC); // TRU device, slave, master
/*Setup GP timer 7 timer used to advance frame by one CS. Add to SetupADC() function after line 91*/
130. *pREG_TIMER0_STOP_CFG_SET = BITM_TIMER_STOP_CFG_TMR07;
131. *pREG_TIMER0_RUN_CLR = BITM_TIMER_RUN_SET_TMR07; /*Disable Timer First*/
132. *pREG_TIMER0_TMR7_CFG = ENUM_TIMER_TMR_CFG_PWMSING_MODE|ENUM_TIMER_TMR_CFG_IRQMODE1 |ENUM_TIMER_TMR_CFG_TRIGSTART | ENUM_TIMER_TMR_CFG_POS_EDGE|ENUM_TIMER_TMR_CFG_PADOUT_EN | ENUM_TIMER_TMR_CFG_EMU_CNT;
133. *pREG_TIMER0_TMR7_DLY = (uint32_t)(fsysclk / F_SW - 0.00000045 * fsysclk); /* Delay must be Tsw minus one ADC chip-select. Chip select is 18 ACLKs*/
134. *pREG_TIMER0_TMR7_WID = 16; /*Be careful here... DLY+WID must be smaller than one PWM period. In other words, WID must be smaller than one ADC chip select. If WID>CS, trigger pulse stretches into next PWM period. */
135. *pREG_TIMER0_TRG_MSK &= ~(BITM_TIMER_TRG_MSK_TMR07);
136. *pREG_TIMER0_TRG_IE |= BITM_TIMER_TRG_IE_TMR07; /*Enable TMR7*/
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