介紹了Arria II GX FPGA亮點，高速收發(fā)器特性，Arria II GX FPGA架構(gòu)以及Arria II GX FPGA 開發(fā)套件主要特性，開發(fā)板方框圖，詳細(xì)的開發(fā)板電路圖和材料清單（BOM）。

Arria II FPGAs: Cost-Optimized, Lowest Power 6G Transceiver FPGAs

The Arria? II GX device family is designed specifically for ease-of-use. The cost-optimized, 40-nm device family architecture features a low-power, programmable logic engine and streamlined transceivers and I/Os. Common interfaces, such as the Physical Interface for PCI Express? (PIPE) (PCIe?), Ethernet, and DDR3 memory are easily implemented in your design with the Quartus? II software, the SOPC Builder design software, and a broad library of hard and soft intellectual property (IP) solutions from Altera?. The Arria II GX device family makes designing for applications requiring transceivers operating at up to 6.375 Gbps fast and easy.

Arria II GX FPGA亮點：

The Arria II GX device features consist of the following highlights:

■ 40-nm, low-power FPGA engine

■ Adaptive logic module (ALM) offers the highest logic efficiency in the industry

■ Eight-input fracturable look-up table (LUT)

■ Memory logic array blocks (MLABs) for efficient implementation of small FIFOs

■ High-performance digital signal processing (DSP) blocks up to 380 MHz

■ Configurable as 9 × 9-bit, 12 × 12-bit, 18 × 18-bit, and 36 × 36-bit full-precision multipliers as well as 18 × 36-bit high-precision multiplier

■ Hardcoded adders, subtractors, accumulators, and summation functions

■ Fully-integrated design flow with the MATLAB and DSP Builder software from Altera

■ Maximum system bandwidth

■ Up to 16 full-duplex clock data recovery (CDR)-based transceivers supporting rates between 155 Mbps and 6.375 Gbps

■ Dedicated circuitry to support physical layer functionality for popular serial protocols, including PCIe Gen1, Gbps Ethernet, Serial RapidIO? (SRIO), Common Public Radio Interface (CPRI), OBSAI, SD/HD/3G/ASI Serial Digital Interface (SDI), XAUI, HiGig/HiGig+, SATA/Serial Attached SCSI (SAS), GPON, SerialLite II, Fiber Channel, and SONET/SDH

■ Complete PIPE protocol solution with an embedded hard IP block that provides physical interface and media access control (PHY/MAC) layer, Data Link layer, and Transaction layer functionality

■ Optimized for high-bandwidth system interfaces

■ Up to 612 user I/O pins arranged in up to 12 modular I/O banks that support a wide range of single-ended and differential I/O standards

■ High-speed LVDS I/O support with serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry at data rates from 150 Mbps to 1.25 Gbps

■ Low power

■ Patented architectural power reduction techniques

■ Per-channel transceiver power consumption is approximately 100 mW under typical conditions at 3.125 Gbps

■ Power optimizations integrated into the Quartus II development software

■ Advanced usability and security features

■ Parallel and serial configuration options

■ On-chip series termination (RS OCT) and differential I/O termination

■ 256-bit advanced encryption standard (AES) programming file encryption for design security with volatile and non-volatile key storage options

■ Robust portfolio of IP for processing, serial protocols, and memory interfaces

■ Low cost, easy-to-use development kits featuring high-speed mezzanine connectors (HSMC) Emulated LVDS output support with a data rate of up to 945 Mbps

高速收發(fā)器特性：

High-Speed Transceiver Features

Arria II GX devices integrate up to 16 transceivers on a single device. The transceiver

block is optimized for cost and power consumption. Arria II GX transceivers support the following features:

■ Configurable pre-emphasis and equalization, and adjustable output differential voltage

■ Flexible and easy-to-configure transceiver datapath to implement proprietary protocols

■ Signal integrity features

■ Programmable transmitter pre-emphasis to compensate for inter-symbol interference (ISI)

■ User-controlled five-stage receiver equalization with up to 7 dB of high-frequency gain

■ On-die power supply regulators for transmitter and receiver PLL charge pump and voltage-controlled oscillator (VCO) for superior noise immunity

■ Calibration circuitry for transmitter and receiver on-chip termination (OCT) resistors

■ Diagnostic features

■ Serial loopback from the transmitter serializer to the receiver CDR for transceiver physical coding sublayer (PCS) and physical media attachment (PMA) diagnostics

■ Parallel loopback from the transmitter PCS to the receiver PCS with built-in self test (BIST) pattern generator and verifier

■ Reverse serial loopback pre- and post-CDR to transmitter buffer for physical link diagnostics

■ Loopback master and slave capability in PCIe hard IP blocks

■ Support for protocol features such as MSB-to-LSB transmission in a SONET/SDH configuration and spread-spectrum clocking in a PCIe Configuration

Arria II GX Device Features

圖1。Arria II GX FPGA架構(gòu)

Arria II GX and GZ FPGAs are backed by intellectual property (IP) functions, design guidelines, and collateral to help you design with ease in several market segments, including:

Wireless

Wireline

Broadcast

Military

Arria II GX FPGA 開發(fā)套件

The Altera^? Arria^? II GX FPGA Development Kit delivers a complete system-level design environment that includes both the hardware and software needed to immediately begin developing FPGA designs. With this PCI-SIG-compliant board and a one-year license for Quartus^? II design software, you can:

Develop and test PCI Express 1.0 (up to x8 lane) designs

Develop and test memory subsystems consisting of DDR2 and/or?DDR3 memory

Develop and test designs?based on other?Arria II?GX supported protocol interfaces such as Gigabit Ethernet, SDI, CPRI, OBSAI, SAS/SATA, and Serial RapidIO^?.^? Many?of these are supported?by taking advantage of this board＇s modular capability through the high-speed mezzanine card (HSMC) connectors?and?over 20 different HSMC connectors?available through Altera partners.

開發(fā)套件包括：

Development Kit Contents

The Arria II GX FPGA Development Kit is RoHS compliant and features the following:

Arria II GX EP2AGX125EF35 FPGA in the 1152-pin fine pitch BGA package

124,100 logic elements (LEs)

49,640 adaptive logic modules (ALMs)

8,121 Kb on-chip memory

12 high-speed transceivers

6 phase-locked loops (PLLs)

576 18x18 multipliers

0.9V core power

Max^? II EPM2210F256 CPLD in the 256-pin Fine Pitch BGA Package

2.5V core power

On-board ports

One?HSMC expansion port

One gigabit Ethernet port

On-board memory

128-MB 16-bit DDR3 device

1-GB 64-bit DDR2 SODIMM

2-MB SSRAM

64-MB flash

FPGA configuration circuitry

MAX II CPLD and flash fast passive parallel configuration

On-board USB-Blaster? circuitry using the Quartus II Programmer

On-board clocking circuitry

Four on-board oscillators

100 MHz

Programmable oscillator, default frequency 125 MHz

Programmable oscillator, default frequency 100 MHz

155.52 MHz

SMA connectors for external LVPECL clock input

SMA connector for clock output

General user I/O

LEDs/displays

Four?user LEDs

Two-line character LCD display

One?configuration-done LED

One HSMC interface transmit/receive LED (Tx/Rx)

Three?PCI Express LEDs

Five?Ethernet LEDs

Push-buttons

One?user reset (CPU reset)

One?MAX II CPLD reset

One?load image (program FPGA from flash)

One?image select (select image to load from flash)

Two?general user push-buttons

DIP switches

Four?user DIP switches

Eight?MAX II device control DIP switches

Power supply

14-V to 20-V DC input

PCI Express edge connector power

On-board power measurement circuitry

Mechanical

PCI Express full-length standard-height (8.48” x 4.376”)

PCI Express chassis or bench-top operation

Arria II GX FPGA Development Kit CD-ROM

Design examples

Board Update Portal, featuring the Nios^??II processor web server and remote system update

Board test system

Complete documentation (see Table 2)

Altera＇s complete Design Suite DVD

Quartus II Software Development Kit Edition, includes support for Arria II GX FPGAs

Includes one-year license

Nios II Embedded Design Suite

MegaCore^??IP Library includes PCI Express, Triple Speed Ethernet, SDI, and DDR3 High-Performance Controller IP cores

IP evaluation available through OpenCore Plus

Power adaptor and cables

Arria II GX FPGA?Development Board

圖2。Arria II GX FPGA?開發(fā)板外形圖

圖3。Arria II GX FPGA?開發(fā)板方框圖

圖4。Arria II GX FPGA?開發(fā)板電路圖之一