Luke Miller并非一開始就是HLS（高層次綜合）的倡導者。在使用早期的工具版本的時候，他似乎有過一些糟糕的經歷。他寫道： “……我的心筑起心墻，我需要幫助。”幸運的是，現在的他似乎已經通過了一個12步HLS培訓活動， 現在可以利用Xilinx Vivado HLS有效地開展工作了。

SemiWiki 有了一位新的博主，被稱為“The FPGA Expert（FPGA專家）”。通過LinkedIn簡單搜索，我得知這位FPGA專家是Luke Miller，他最近發表了一篇博文，介紹如何使用高層次綜合（HLS）開發從C到其他HLL版本的各種加速硬件。 雖然不像“手把手的菜譜”那樣具體詳盡，但依然非常有趣。

Miller曾經在IBM公司擔任過ASIC設計師，在Lockheed擔任過硬件師（工程師/架構師），目前是一位擁有軍事和航空設計經驗的PE。Miller的網站名為FPGA Expert，上面有一段特別的講述其個人經歷的視頻，其中描述了多項軍事、航空和醫療項目（飛機、雷達和醫療成像），所以，我猜他應該擁有非常豐富的FPGA設計經驗。他的網站證實了這個猜想。 Miller似乎也非常了解HLS。他寫道：

“設計時間的加速并非從C到VHDL的轉換， 真正起到關鍵因素的是仿真域 —您再也無需通過RTL逐件驗證每項設計。”
Luke Miller并非一直都是HLS（高層次綜合）的倡導者。在使用早期的工具版本的時候，他似乎有些糟糕的經歷。。他寫道：“……我的心筑起心墻，我需要幫助。”幸運的是，他似乎已經通過了一個12步HLS培訓活動， 現在可以通過Xilinx Vivado HLS有效地開展工作了。

點擊此處，閱讀Miller有關HLS的建議：“高層次綜合 —它真的行！ （ High Level Synthesis – It’s for Real） ”%96-%92s-real.html

下面是Miller的全文供參考：

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High Level Synthesis – It’s for Real
by
theFPGAexpert
Published on 04-11-2013 06:30 PM

It was spring 2010 and I was asked to attend an HLS (High Level Synthesis) meeting. To be honest I cringed, after my bad relationship with Accel DSP and broken promises my heart was all walled up and needed counseling. But my management had a way of making me an offer I could not refuse, like keeping my job. So reluctantly I went. Does your employer do lunch and learns instead of real training? You know what that equals right? A 1/8 pay cut, but let’s play nice.

Anyways after the usual introductions at the meeting they began to get into the meat of the tool. I quickly diverted and asked if we could see the tool in action and move away from the power point and boy did they. First up was a cookie cutter FIR filter but it worked, really! Then they moved into floating point designs etc. This HLS was the greatest thing since sliced bread. I saw its potential and I needed to try it. We all agreed on an evaluation period. Now I am by no means the best coder in the world, but even the best would have a hard time beating the HLS tool with respect to design time, area and latency.

What HLS is not: It is not a coder in a box, thus sit down the software guy and have him designing FPGAs. You need to understand the FPGA, no exceptions or you will have a fat, slow design. The C or its variant will need to be restructured, smartly, thus helping the tool out so it can perform better. It is not a button you press and you have a bit image. I know how program managers think.

I leverage HLS tools in this fashion. I view it as Xilinx Corgen on steroids which are driven by a C file. The speed up in design time is not in the translation from C to VHDL but really is in the simulation domain. You are no longer verifying designs piece by piece using RTL. For example, I design a Beamfomer in C. I compile it and then run ‘a.exe’ and verify that the answer matches the expects. That took about a second. For many PRIs of data that could of taken hours in ModelSim. Catching on? I then bring up the HLS tool and pull in the C file and the tool reports the latency, area, clock frequency etc. From that information I can determine which FPGA to use. I then start using directives to optimize the area / latency by using unrolls and pipeline directives. About an hour later my beamformer is done. I then simulate the RTL at my top level but I already know the math works and the tool took care of the boundary conditions. The goal of this article is by no means a recipe on HLS usage but hopefully entices you to check it out, you won’t be sorry.