AM1808 Sitara 處理器

描述

AM1808 ARM微處理器是基于ARM926EJ-S的低功耗應用處理器。

該設備使原始設備制造商（ OEM（原始設計制造商）和原始設計制造商（ODM）通過完全集成的混合處理器解決方案的最大靈活性，快速向市場推出具有強大操作系統支持，豐富用戶界面和高處理性能壽命的設備。

ARM926EJ-S是一個32位RISC處理器內核，可執行32位或16位指令并處理32位，16位或8位數據。核心使用流水線操作，以便處理器和內存系統的所有部分可以連續運行。

ARM內核具有協處理器15（CP15），保護模塊以及數據和程序存儲器管理單元（MMU）表后備緩沖區。 ARM核心處理器具有單獨的16 KB指令和16 KB數據高速緩存。兩者都是與虛擬索引虛擬標記（VIVT）的四向關聯。 ARM內核還具有8KB的RAM（向量表）和64KB的ROM。

外設集包括：具有管理數據輸入/輸出的10/100 Mbps以太網媒體訪問控制器（EMAC）（MDIO））模塊;一個USB2.0 OTG接口;一個USB1.1 OHCI接口;兩個內部集成電路（I ² C Bus）接口;一個多通道音頻串行端口（McASP），帶有16個串行器和FIFO緩沖器;兩個帶有FIFO緩沖器的多通道緩沖串行端口（McBSP）;兩個串行外設接口（SPI），具有多個芯片選擇;四個64位通用定時器，每個都可配置（一個可配置為看門狗）;可配置的16位主機端口接口（HPI）;多達9組通用輸入/輸出（GPIO）引腳，每個引腳包含16個引腳，具有可編程中斷和事件生成模式，與其他外設復用;三個UART接口（每個接口都有 RTS 和 CTS ）;兩個增強型高分辨率脈沖寬度調制器（eHRPWM）外設;三個32位增強型捕獲（eCAP）模塊外設，可配置為3個捕獲輸入或3個輔助脈沖寬度調制器（APWM）輸出;兩個外部存儲器接口;用于較慢存儲器或外設的異步和SDRAM外部存儲器接口（EMIFA）;和更高速的DDR2 /移動DDR控制器。

EMAC在設備和網絡之間提供了有效的接口。 EMAC支持10Base-T和100Base-TX，或半雙工或全雙工模式下的10 Mbps和100 Mbps。此外，MDIO接口可用于PHY配置。 EMAC支持MII和RMII接口。

SATA控制器為海量數據存儲設備提供高速接口。 SATA控制器支持SATA I（1.5 Gbps）和SATA II（3.0 Gbps）。

通用并行端口（uPP）為多種類型的數據轉換器，FPGA或其他并行設備提供高速接口。 uPP支持兩個通道上8到16位的可編程數據寬度。支持單數據速率和雙數據速率傳輸以及START，ENABLE和WAIT信號，以便為各種數據轉換器提供控制。

包含視頻端口接口（VPIF），提供靈活的視頻I /O端口。

豐富的外設集可以控制外部外圍設備并與外部處理器通信。有關每個外設的詳細信息，請參閱本文檔中的相關章節以及相關的外設參考指南。

該器件具有一整套用于ARM處理器的開發工具。這些工具包括C編譯器和調度，以及用于查看源代碼執行情況的Windows調試器界面。

特性

375- and 456-MHz ARM926EJ-S RISC MPU
ARM926EJ-S Core
- 32-Bit and 16-Bit (Thumb) Instructions
- Single-Cycle MAC
- ARM Jazelle Technology
- Embedded ICE-RT for Real-Time Debug
ARM9 Memory Architecture
- 16KB of Instruction Cache
- 16KB of Data Cache
- 8KB of RAM (Vector Table)
- 64KB of ROM
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Channel Controllers
- 3 Transfer Controllers
- 64 Independent DMA Channels
- 16 Quick DMA Channels
- Programmable Transfer Burst Size
128KB of On-Chip Memory
1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
Two External Memory Interfaces:
- EMIFA
  - NOR (8- or 16-Bit-Wide Data)
  - NAND (8- or 16-Bit-Wide Data)
  - 16-Bit SDRAM with 128-MB Address Space
- DDR2/Mobile DDR Memory Controller with one of the following:
  - 16-Bit DDR2 SDRAM with 256-MB Address Space
  - 16-Bit mDDR SDRAM with 256-MB Address Space
Three Configurable 16550-Type UART Modules:
- With Modem Control Signals
- 16-Byte FIFO
- 16x or 13x Oversampling Option
LCD Controller
Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces
Two Master and Slave Inter-Integrated Circuits
(I²C Bus)
One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Real-Time Unit (PRU) Cores
  - 32-Bit Load-Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled via Software to Save Power
  - Register 30 of Each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
USB 1.1 OHCI (Host) with Integrated PHY (USB1)
USB 2.0 OTG Port with Integrated PHY (USB0)
- USB 2.0 High- and Full-Speed Client
- USB 2.0 High-, Full-, and Low-Speed Host
- End Point 0 (Control)
- End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
One Multichannel Audio Serial Port (McASP):
- Transmit and Receive Clocks
- Two Clock Zones and 16 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable
- FIFO Buffers for Transmit and Receive
Two Multichannel Buffered Serial Ports (McBSPs):
- Transmit and Receive Clocks
- Supports TDM, I2S, and Similar Formats
- AC97 Audio Codec Interface
- Telecom Interfaces (ST-Bus, H100)
- 128-Channel TDM
- FIFO Buffers for Transmit and Receive
10/100 Mbps Ethernet MAC (EMAC):
- IEEE 802.3 Compliant
- MII Media-Independent Interface
- RMII Reduced Media-Independent Interface
- Management Data I/O (MDIO) Module
Video Port Interface (VPIF):
- Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
- Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
Universal Parallel Port (uPP):
- High-Speed Parallel Interface to FPGAs and Data Converters
- Data Width on Both Channels is 8- to 16-Bit Inclusive
- Single-Data Rate or Dual-Data Rate Transfers
- Supports Multiple Interfaces with START, ENABLE, and WAIT Controls
Serial ATA (SATA) Controller:
- Supports SATA I (1.5 Gbps) and SATA II
  (3.0 Gbps)
- Supports all SATA Power-Management Features
- Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries
- Supports Port Multiplier and Command-Based Switching
Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
- 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Time-Stamps
361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
361-Ball Pb-Free PBGA [ZWT Suffix], 0.80-mm Ball Pitch
Commercial or Extended Temperature

參數與其它產品相比 AM1x


Arm MHz (Max.)
DRAM
Display
USB
EMAC
SPI
I2C
UART
Operating Temperature Range (C)
Approx. Price (US$)

AM1808	AM1802	AM1806	AM1810
375 456	300	375 456	375 456
DDR2 LPDDR	DDR2 LPDDR	DDR2 LPDDR	DDR2 LPDDR
1 LCD		1 LCD	1 LCD
1	1	1	1
10/100	10/100		10/100
2	2	2	2
2	1	2	2
3	3	3	3
0 to 90 -40 to 105 -40 to 90	-40 to 90	-40 to 105 0 to 90 -40 to 90	-40 to 105
9.28 \| 1ku	8.25 \| 1ku	8.36 \| 1ku	18.53 \| 1ku
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