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TMS320VC5510A 定點數字信號處理器

數據:

描述

The TMS320VC5510/5510A (5510/5510A) fixed-point digital signal processors (DSPs) are based on the TMS320C55x DSP generation CPU processor core. The C55x™;DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU.

The C55x™; DSP generation supports a variable byte width instruction set for improved code density. The instruction unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the program unit (PU). The program unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The 5510/5510A also includes a 24K-byte instruction cache to minimize external memory accesses, improving data throughput and conserving system power.

The 5510/5510A peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst SRAM. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (EHPI) is a 16-bit parallel interface used to provide host processor access to internal memory on the 5510/5510A. The EHPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wider variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, eight general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.

The 5510/5510A is supported by the industry?s leading eXpressDSP™; software environment including the Code Composer Studio™; integrated development environment, DSP/BIOS™; software kernel foundation, the TMS320™; DSP Algorithm Standard, and the industry?s largest third-party network. Code Composer Studio features code generation tools including a C-Compiler, Visual Linker, simulator, Real-Time Data Exchange (RTDX™;), XDS510™; emulation device drivers, and Chip Support Libraries (CSL). DSP/BIOS is a scalable real-time software foundation available for no cost to users of Texas Instruments? DSP products providing a pre-emptive task scheduler and real-time analysis capabilities with very low memory and megahertz overhead. The TMS320 DSP Algorithm Standard is a specification of coding conventions allowing fast integration of algorithms from different teams, sites, or third parties into the application framework. Texas Instruments? extensive DSP third-party network of over 400 providers brings focused competencies and complete solutions to customers.

Texas Instruments (TI) has also developed foundation software available for the 5510/5510A. The C55x DSP Library (DSPLIB) features over 50 C-callable software kernels (FIR/IIR filters, Fast Fourier Transforms (FFTs), and various computational functions). The DSP Image/Video Processing Library (IMGLIB) contains over 20 software kernels highly optimized for C55x DSPs and is compiled with the latest revision of the C55x DSP code generation tools. These imaging functions support a wide range of applications that include compression, video processing, machine vision, and medical imaging.

The TMS320C55x DSP core was created with an open architecture that allows the addition of application-specific hardware to boost performance on specific algorithms. The hardware extensions on the 5510/5510A strike the perfect balance of fixed function performance with programmable flexibility, while achieving low-power consumption, and cost that traditionally has been difficult to find in the video-processor market. The extensions allow the 5510/5510A to deliver exceptional video codec performance with more than half its bandwidth available for performing additional functions such as color space conversion, user-interface operations, security, TCP/IP, voice recognition, and text-to-speech conversion. As a result, a single 5510/5510A DSP can power most portable digital video applications with processing headroom to spare. For more information, see the TMS320C55x Hardware Extensions for Image/Video Applications Programmer?s Reference (literature number SPRU098). For more information on using the the DSP Image Processing Library, see the TMS320C55x Image/Video Processing Library Programmer?s Reference (literature number SPRU037).

特性

  • 高性能,低功耗,定點TMS320C55x™;數字信號處理器(DSP)
    • 6.25- /5-ns指令周期時間
    • 160- /200-MHz時鐘速率
    • 每個周期執行一個/兩個指令
    • 雙乘法器(每秒累計高達4億次(MMACS))
    • 兩個算術/邏輯單元
    • 一個內部程序總線
    • 三個內部數據/操作數讀總線
    • 兩個內部數據/操作數寫總線
  • 指令高速緩存(24K字節)
  • < li> 160K x 16位片上RAM組成:
    • 八塊4K×16位雙存取RAM(DARAM)(64K字節)
    • 32塊4K ×16位單訪問RAM(SARAM)(256K字節)
  • 16K×16位片上ROM(32K字節)
  • 8M×16位最大可尋址外部存儲空間
  • 32位外部存儲器接口(EMIF),帶無線接口:
    • 異步靜態RAM(SRAM)
    • 異步EPROM
    • 同步DRAM(SDRAM)
    • 同步突發SRAM(SBSRAM)
  • 六個器件功能域的可編程低功耗控制
  • 片上外設
    • 兩個20位定時器
    • 六通道直接存儲器訪問(DMA)控制器
    • 三個多通道緩沖串行端口(McBSP)
    • 16位并行增強型主機端口接口(EHPI)
    • 可編程數字鎖相環路(DPLL)時鐘發生器
    • 八個通用I /O(GPIO)引腳和專用通用輸出(XF)
  • 開 - 基于芯片掃描的仿真邏輯
  • IEEE Std 1149.1 (JTAG)邊界掃描邏輯
  • 240端子MicroStar BGA™; (球柵陣列)(GGW后綴)
  • 240端子MicroStar BGA™; (球柵陣列)(ZGW后綴)[無鉛]
  • 3.3-VI /O電源電壓
  • 1.6V核電源電壓
< p> TMS320C55x和MicroStar BGA是德州儀器公司的商標。
其他商標是其各自所有者的財產。
IEEE標準1149.1-1990標準測試訪問端口和邊界掃描架構。
C55x,eXpressDSP,Code Composer Studio,DSP /BIOS,TMS320,RTDX和XDS510是德州儀器公司的商標。

參數 與其它產品相比 C55x DSP

 
DSP
DSP MHz (Max)
DRAM
Other Hardware Acceleration
USB
SPI
I2C
UART (SCI)
Operating Temperature Range (C)
Applications
Operating Systems
McBSP
HPI
TMS320VC5510A
1 C55x    
160
200    
SDRAM    
N/A    
0    
0    
0    
0    
-40 to 85
0 to 85    
Audio
Automotive
Communications and Telecom
Consumer Electronics
Industrial    
DSP/BIOS
VLX    
3    
1 16-bit HPI    

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