Memory Compiler
M31 memory compilers are designed with high industrial standards to which provides the memory solutions for density, power, and performance optimizations. M31 memory compilers are using leveraging industry-leading techniques to help customers to achieve their various SoC projects.
Meanwhile, M31 memory compiler IP was certified with ASIL-D of ISO 26262 in April, 2019.
Compiler Types
Instance Types
Features
- High-sigma design for yield and performance optimization
- Ultra-high-speed techniques for Cache implementation
- Ultra-low-power circuits for mobile and AIoT devices
- Ultra-high-density memory design for consumer solutions
- Provides multi-port memory design for different processors application
- Apply the Dynamic Voltage/Frequency scaling (DVFS) technique for users with multi-VDD domain
- Specific option pins for dynamic/standby power gating
- Porosity top metal lines structure to improve customer’s chip routability
- Synchronous read/write operations
- Different VT of periphery devices options
- Flexible bank structure for performance and power optimization
- Specialty power gating for performance and power optimization
- Separate dual rail design of VCCA(array) and VCCP(periphery)
- Separate read/write margin for sigma coverage design
- Separate read/write-assist strength for different accumulated density applications
- BIST [ON/OFF]; Scan [ON/OFF];
- Provides row/col-redundancy [ON/OFF]Different VT of periphery devices options
