具有 3 個 LVDS 和 5 個 LVPECL 輸出的 1.6GHz 高性能時鐘緩沖器、分頻器和分配器
30 fs additive jitter (100 Hz to 20 MHz) Dual clock inputs Programmable output channels (0 to 1600 MHz) External synchronization Pin compatible family of clocking devices 3.15 to 3.45 V operation Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
High performance Clock Distribution Wireless Infrastructure Medical Imaging Wired Communications Test and Measurement Military / Aerospace
| Function | Differential, Fanout |
| Additive RMS jitter (Typ) (fs) | 30 |
| Output frequency (Max) (MHz) | 1600 |
| Number of outputs | 8 |
| Output supply voltage (V) | 3.3 |
| Core supply voltage (V) | 3.3 |
| Output skew (ps) | 30 |
| Features | uWire |
| Operating temperature range (C) | -40 to 85 |
| Rating | Catalog |
| Output type | LVDS, LVPECL |
| Input type | LVDS |
| Device | LVDS | LVPECL |
|---|---|---|
| LMK01000 | 3 | 5 |
| LMK01010 | 8 | 0 |
| LMK01020 | 0 | 8 |
The LMK01000 family provides an easy way to divide and distribute high performance clock signals throughout the system. These devices provide best-in-class noise performance and are designed to be pin-to-pin and footprint compatible with LMK03000/LMK02000 family of precision clock conditioners.
The LMK01000 family features two programmable clock inputs (CLKin0 and CLKin1) that allow the user to dynamically switch between different clock domains.
Each device features 8 clock outputs with independently programmable dividers and delay adjustments. The outputs of the device can be easily synchronized by an external pin (SYNC*).
Target Applications
