| Function | Single-ended |
| Additive RMS jitter (Typ) (fs) | 40 |
| Output frequency (Max) (MHz) | 200 |
| Number of outputs | 10 |
| Output supply voltage (V) | 2.5, 3.3 |
| Core supply voltage (V) | 2.5, 3.3 |
| Output skew (ps) | 100 |
| Features | Pin control |
| Operating temperature range (C) | -40 to 85 |
| Rating | Catalog |
| Output type | LVTTL |
| Input type | LVTTL |
- High-Performance 1:10 Clock Driver
- Pin-to-Pin Skew < 100 ps at VDD 3.3 V
- VDD Range = 2.3 V to 3.6 V
- Input Clock Up To 200 MHz (See Figure 7)
- Operating Temperature Range -40°C to 85°C
- Output Enable Glitch Suppression
- Distributes One Clock Input to Two Banks of Five Outputs
- Packaged in 24-Pin TSSOP
- Pin-to-Pin Compatible to the CDCVF2310,
Except the R = 22-
Series Damping
Resistors at Yn - APPLICATIONS
- General-Purpose Applications
The CDCVF310 is a high-performance, low-skew clock bufferthat operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.
The CDCVF310 is characterized for operation from -40°C to 85°C.
