| Sample rate (Max) (MSPS) | 200 |
| Resolution (Bits) | 10 |
| Number of input channels | 2 |
| Interface type | Parallel CMOS, Parallel LVDS |
| Analog input BW (MHz) | 900 |
| Features | Low Power |
| Rating | Catalog |
| Input range (Vp-p) | 1.5 |
| Power consumption (Typ) (mW) | 450 |
| Architecture | Pipeline |
| SNR (dB) | 59.9 |
| ENOB (Bits) | 9.65 |
| SFDR (dB) | 82 |
| Operating temperature range (C) | -40 to 85 |
| Input buffer | No |
- Single 1.8V Power Supply Operation.
- Power Scaling with Clock Frequency.
- Internal Sample-and-Hold.
- Internal or External Reference.
- Power Down Mode.
- Offset Binary or 2's Complement Output Data Format.
- LVDS or CMOS Output Signals.
- 60-pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)
- Clock Duty Cycle Stabilizer.
- IF Sampling Bandwidth > 900MHz.
Key Specifications
- Resolution 10 Bits
- Conversion Rate 200 MSPS
- ENOB 9.6 bits (typ) @Fin=70 MHz
- SNR 59.9 dBFS (typ) @Fin=70 MHz
- SINAD 59.9 dBFS (typ) @Fin=70 MHz
- SFDR 82 dBFS (typ) @Fin=70 MHz
- LVDS Power 450mW (typ) @Fs=200 MSPS
- CMOS Power 280mW (typ) @Fs=170 MSPS
- Operating Temp. Range ?40°C to +85°C.
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The ADC10DV200 is a monolithic analog-to-digital converter capable of converting two analog input signals into 10-bit digital words at rates up to 200 Mega Samples Per Second (MSPS). The digital output mode is selectable and can be either differential LVDS or CMOS signals. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 900MHz. Fabricated in core CMOS process, the ADC10DV200 may be operated from a single 1.8V power supply. The ADC10DV200 achieves approximately 9.6 effective bits at Nyquist and consumes just 280mW at 170MSPS in CMOS mode and 450mW at 200MSPS in LVDS mode. The power consumption can be scaled down further by reducing sampling rates.
