| Sample rate (Max) (MSPS) | 60 |
| Resolution (Bits) | 8 |
| Number of input channels | 1 |
| Interface type | Parallel CMOS, TTL |
| Analog input BW (MHz) | 270 |
| Features | Low Power |
| Rating | Catalog |
| Input range (Vp-p) | 1.6 |
| Power consumption (Typ) (mW) | 53 |
| Architecture | Pipeline |
| SNR (dB) | 48 |
| ENOB (Bits) | 7.6 |
| SFDR (dB) | 59.1 |
| Operating temperature range (C) | -40 to 85 |
| Input buffer | No |
- Single-ended input
- Internal sample-and-hold function
- Low voltage (single +3V) operation
- Small package
- Power-down feature
All trademarks are the property of their respective owners.
Key Specifications
- Resolution 8 bits
- Conversion rate 60 MSPS
- DNL ±0.25 LSB (typ)
- INL +0.5/?0.2 LSB (typ)
- SNR (10.1 MHz) 48 dB (typ)
- ENOB (10.1 MHz) 7.6 bits (typ)
- THD (10.1 MHz) ?57 dB (typ)
- Latency 5 Clock Cycles
- No missing codes Ensured
- Power Consumption
- Operating 0.65 mW/MSPS (typ)
- Power Down Mode 1.0 mW (typ)
The ADC08L060 is a low-power, 8-bit, monolithic analog-to-digital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use, this product operates at conversion rates of 10 MSPS to 60 MSPS while consuming just 0.65 mW per MHz of clock frequency, or 39 mW at 60 MSPS. Raising the PD pin puts the ADC08L060 into a Power Down mode where it consumes about 1 mW.
The unique architecture achieves 7.6 Effective Bits. The ADC08L060 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08L060s reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 1.8V to 3V logic. The output coding is straight binary and the digital inputs (CLK and PD) are TTL/CMOS compatible.
The ADC08L060 is offered in a 24-lead plastic package (TSSOP) and is specified over the industrial temperature range of ?40°C to +85°C.
