| Resolution (Bits) | 14 |
| Number of input channels | 4 |
| Sample rate (Max) (kSPS) | 200 |
| Interface type | SPI |
| Architecture | SAR |
| Input type | Pseudo-Differential, Single-Ended |
| Multi-channel configuration | Multiplexed |
| Rating | Catalog |
| Reference mode | Ext, Int |
| Input range (Max) (V) | 5 |
| Input range (Min) (V) | 0 |
| Features | Oscillator |
| Operating temperature range (C) | -40 to 85, 0 to 70 |
| Power consumption (Typ) (mW) | 20 |
| Analog voltage AVDD (Min) (V) | 4.5 |
| SNR (dB) | 81 |
| Analog voltage AVDD (Max) (V) | 5.5 |
| INL (Max) (+/-LSB) | 0.8 |
| Digital supply (Min) (V) | 2.7 |
| Digital supply (Max) (V) | 5.5 |
- 14-Bit Resolution
- Maximum Throughput 200 KSPS
- Analog Input Range 0-V to Reference Voltage
- Multiple Analog Inputs:
- 8 Channels for TLC3548
- 4 Channels for TLC3544
- Pseudodifferential Analog Inputs
- SPI/DSP-Compatible Serial Interfaces With SCLK up to 25 MHz
- Single 5-V Analog Supply; 3-/5-V Digital Supply
- Low Power:
- 4 mA (Internal Reference: 1.8 mA) for Normal Operation
- 20 μA in Autopower-Down
- Built-In 4-V Reference, Conversion Clock and 8x FIFO
- Hardware-Controlled and Programmable Sampling Period
- Programmable Autochannel Sweep and Repeat
- Hardware Default Configuration
- INL: ±1 LSB Max
- DNL: ±1 LSB Max
- SINAD: 80.8 dB
- THD: –95 dB
The TLC3544 and TLC3548 are a family of 14-bit resolution high-performance, low-power, CMOS analog-to-digital converters (ADC). All devices operate from a single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital inputs [chip select (CS\), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS\ (works as SS\, slave select), SDI, SDO, and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form a DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS\ works as the chip select to allow the host DSP to access the individual converter. CS\ can be tied to ground if only one converter is used. FS must be tied to DVDD if it is not used (such as in an SPI interface). When SDI is tied to DVDD, the device is set in hardware default mode after power-on, and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS\ or FS) are needed to interface with the host.
In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK (normal sampling) or can be controlled by CSTART\ to extend the sampling period (extended sampling). The normal sampling period can also be programmed as short sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular among high-performance signal processors. The TLC3544 and TLC3548 are designed to operate with low power consumption. The power saving feature is further enhanced with software power-down/ autopower-down modes and programmable conversion speeds. The conversion clock (internal OSC) is built in. The converter can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3544 and TLC3548 have a 4-V internal reference. The converters are specified with unipolar input range of 0-V to 5-V when a 5-V external reference is used.
