| Technology Family | AHC |
| Supply voltage (Min) (V) | 2 |
| Supply voltage (Max) (V) | 5.5 |
| Number of channels (#) | 6 |
| IOL (Max) (mA) | 8 |
| ICC (Max) (uA) | 40 |
| IOH (Max) (mA) | -8 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Features | Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs |
| Rating | Catalog |
- Operating Range 2-V to 5.5-V V CC
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
The ?AHC367 devices are hex buffers and line drivers designed for 2-V to 5.5-V VCC operation.
These devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ?AHC367 devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE\ and 2OE\) inputs. When OE\ is low, the device passes noninverted data from the A inputs to the Y outputs. When OE\ is high, the utputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
