Automotive 8-bit parallel-out serial shift registers
| Configuration | Serial-in, Parallel-out |
| Bits (#) | 8 |
| Technology Family | HCS |
| Supply voltage (Min) (V) | 2 |
| Supply voltage (Max) (V) | 6 |
| Input type | Schmitt-Trigger |
| Output type | Push-Pull |
| Clock Frequency (MHz) | 62 |
| IOL (Max) (mA) | 7.8 |
| IOH (Max) (mA) | -7.8 |
| ICC (Max) (uA) | 2 |
| Features | Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode |
- AEC-Q100 Qualified for automotive applications:
- Device temperature grade 1: –40°C to +125°C, TA
- Device HBM ESD Classification Level 2
- Device CDM ESD Classifcation Level C6
- Wide operating voltage range: 2 V to 6 V
- Schmitt-trigger inputs allow for slow or noisy input signals
- Low power consumption
- Typical ICC of 100 nA
- Typical input leakage current of ±100 nA
- 7.8-mA output drive at 6 V
The device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. Data at the serial inputs can be changed while CLK is high or low, provided the minimum setup time requirements are met. All inputs include Schmitt-trigger architecture, adding noise margin and eliminating any input transition rate requirement. Clocking occurs on the low-to-high-level transition of CLK.
Upon a clock trigger, the device will store the result of the (A ● B) input data line in the first register and propagate each register’s data to the next register. The outputs are inverted from the data stored.
