具有清零端的四路 D 型觸發器
| Number of channels (#) | 4 |
| Technology Family | LV-A |
| Supply voltage (Min) (V) | 2 |
| Supply voltage (Max) (V) | 5.5 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Clock Frequency (Max) (MHz) | 70 |
| IOL (Max) (mA) | 12 |
| IOH (Max) (mA) | -12 |
| ICC (Max) (uA) | 20 |
| Features | Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) |
- 2-V to 5.5-V VCC Operation
- Max tpd of 7.5 ns at 5 V
- Typical VOLP (Output Ground Bounce)
??? <0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
??? >2.3 V at VCC = 3.3 V, TA = 25°C - Support Mixed-Mode Voltage Operation on All Ports
- Contain Four Flip-Flops With Double-Rail Outputs
- Applications Include:
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
The 'LV175A devices are quadruple D-type flip-flops designed for 2-V to 5.5-V VCC operation.
These devices have a direct clear (CLR\) input and feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
