| Arm CPU | 1 Arm Cortex-A8 |
| Arm MHz (Max.) | 1200 |
| CPU | 32-bit |
| Display type | 2 LCD, 1 HDMI |
| Ethernet MAC | 1-Port 10/100/1000 |
| PCIe | 1 PCIe Gen 2 |
| Security | Cryptography |
| Rating | Catalog |
| Operating temperature range (C) | 0 to 95 |
- High-Performance Sitara ARM Microprocessors (MPUs)
- ARMCortex-A8 RISC Processor
- Up to 1.20 GHz
- ARMCortex-A8 RISC Processor
- ARM Cortex-A8 Core
- ARMv7 Architecture
- In-Order, Dual-Issue, Superscalar Processor Core
- NEON Multimedia Architecture
- Supports Integer and Floating Point (VFPv3-IEEE754 Compliant)
- Jazelle RCT Execution Environment
- ARMv7 Architecture
- ARM Cortex-A8 Memory Architecture
- 32-KB Instruction and Data Caches
- 256-KB L2 Cache
- 64-KB RAM, 48-KB of Boot ROM
- 512KB of On-Chip Memory Controller (OCMC) RAM
- SGX530 3D Graphics Engine (Available Only on the AM3894 Device)
- Delivers up to 30 MTriangles per Second
- Universal Scalable Shader Engine
- Direct3D Mobile, OpenGL ES 1.1 and 2.0, OpenVG 1.1, OpenMax API Support
- Advanced Geometry DMA Driven Operation
- Programmable HQ Image Anti-Aliasing
- Endianness
- ARM Instructions and Data – Little Endian
- HD Video Processing Subsystem (HDVPSS)
- Two 165-MHz HD Video Capture Channels
- One 16-Bit or 24-Bit and One 16-Bit Channel
- Each Channel Splittable Into Dual 8-Bit Capture Channels
- Two 165-MHz HD Video Display Channels
- One 16-Bit, 24-Bit, 30-Bit Channel and One 16-Bit Channel
- Simultaneous SD and HD Analog Output
- Digital HDMI 1.3 Transmitter with PHY with HDCP up to 165-MHz Pixel Clock
- Three Graphics Layers
- Two 165-MHz HD Video Capture Channels
- Dual 32-Bit DDR2 and DDR3 SDRAM Interfaces
- Supports up to DDR2-800 and DDR3-1600
- Up to Eight x8 Devices Total
- 2GB of Total Address Space
- Dynamic Memory Manager (DMM)
- Programmable Multi-Zone Memory Mapping and Interleaving
- Enables Efficient 2D Block Accesses
- Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
- Optimizes Interlaced Accesses
- One PCI Express (PCIe) 2.0 Port with Integrated PHY
- Single Port with 1 or 2 Lanes at 5.0 GT per Second
- Configurable as Root Complex or Endpoint
- Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHYs
- Direct Interface for Two Hard Disk Drives
- Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
- Supports Port Multiplier and Command-Based Switching
- Two 10 Mbps, 100 Mbps, and 1000 Mbps Ethernet MACs (EMAC)
- IEEE 802.3 Compliant (3.3-V I/O Only)
- MII and GMII Media Independent Interfaces
- Management Data I/O (MDIO) Module
- Dual USB 2.0 Ports with Integrated PHYs
- USB 2.0 High-Speed and Full-Speed Client
- USB 2.0 High-Speed, Full-Speed, and Low-Speed Host
- Supports Endpoints 0-15
- General-Purpose Memory Controller (GPMC)
- 8-Bit and 16-Bit Multiplexed Address and Data Bus
- Up to 6 Chip Selects with up to 256-MB Address Space per Chip Select Pin
- Glueless Interface to NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection), SRAM and Pseudo-SRAM
- Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit and 512-Byte Hardware ECC for NAND
- Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs
- Enhanced Direct-Memory-Access (EDMA) Controller
- Four Transfer Controllers
- 64 Independent DMA Channels and 8 Quick DMA (QDMA) Channels
- Seven 32-Bit General-Purpose Timers
- One System Watchdog Timer
- Three Configurable UART, IrDA, and CIR Modules
- UART0 with Modem Control Signals
- Supports up to 3.6864 Mbps UART
- SIR, MIR, FIR (4.0 MBAUD), and CIR
- One 40-MHz Serial Peripheral Interface (SPI) with Four Chip Selects
- SD and SDIO Serial Interface (1-Bit and 4-Bit)
- Dual Inter-Integrated Circuit (I2C bus) Ports
- Three Multichannel Audio Serial Ports (McASPs)
- One Six-Serializer Transmit and Receive Port
- Two Dual-Serializer Transmit and Receive Ports
- DIT-Capable For SDIF and PDIF (All Ports)
- Multichannel Buffered Serial Port (McBSP)
- Transmit and Receive Clocks up to 48 MHz
- Two Clock Zones and Two Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- Real-Time Clock (RTC)
- One-Time or Periodic Interrupt Generation
- Up to 64 General-Purpose I/O (GPIO) Pins
- On-Chip ARM ROM Bootloader (RBL)
- Power, Reset, and Clock Management
- SmartReflex Technology (Level 2)
- Seven Independent Core Power Domains
- Clock Enable and Disable Control For Subsystems and Peripherals
- IEEE 1149.1 (JTAG) and IEEE 1149.7 (cJTAG) Compatible
- Via Channel Technology Enables use of
0.8-mm Design Rules - 40-nm CMOS Technology
- 3.3-V Single-Ended LVCMOS I/Os (Except for DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN at 1.8 V)
The AM389x Sitara ARM processors are a highly integrated, programmable platform that leverages TI's Sitara technology to meet the processing needs of the following applications: single-board computing, network and communications processing, industrial automation, human machine interface, and interactive point-of-service kiosks.
The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device combines high-performance ARM processing with a highly integrated peripheral set.
The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache; and 64KB of RAM.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD video processing subsystem (HDVPSS), which provides output of simultaneous HD and SD analog video and dual HD video inputs; up to two Gigabit Ethernet MACs (10 Mbps,100, Mbps, 1000 Mbps) with GMII and MDIO interface; two USB ports with integrated 2.0 PHY; PCIe port x2 lanes GEN2 compliant interface, which allows the device to act as a PCIe root complex or device endpoint; one 6-channel McASP audio serial port (with DIT mode); two dual-channel McASP audio serial ports (with DIT mode); one McBSP multichannel buffered serial port; three UARTs with IrDA and CIR support; SPI serial interface; SD and SDIO serial interface; two I2C master and slave interfaces; up to 64GPIO pins; seven 32-bit timers; system watchdog timer; dual DDR2 and DDR3 SDRAM interface; flexible 8-bit and 16-bit asynchronous memory interface; and up to two SATA interfaces for external storage on two disk drives or more with the use of a port multiplier.
The device also includes an SGX530 3D graphics engine (available only on the AM3894 device) to off-load many video and imaging processing tasks from the core. Additionally, the device has a complete set of development tools for the ARM, including Ccompilers and a Microsoft Windows debugger interface for visibility into source code execution.
The device package has been specially engineered with Via Channel technology. This technology allows use of 0.8-mm pitch PCB feature sizes in this 0.65-mm pitch package, and substantially reduces PCB costs. Via Channel technology also allows PCB routing in only two signal layers due to the increased layer efficiency of the Via Channel BGA technology.
