軍用級 C80x 定點 DSP
| DSP | 1 C2x |
| DSP MHz (Max) | 50 |
| CPU | 32-bit |
| Rating | Military |
| Operating temperature range (C) | -55 to 125 |
- Single-Chip Parallel Multiple Instruction/Multiple Data (MIMD) Digital Signal Processor (DSP)
- More Than Two Billion RISC-Equivalent Operations per Second
- Master Processor (MP)
- 32-Bit Reduced Instruction Set Computing (RISC) Processor
- IEEE-754 Floating-Point Capability
- 4K-Byte Instruction Cache
- 4K-Byte Data Cache
- Four Parallel Processors (PP)
- 32-Bit Advanced DSPs
- 64-Bit Opcode Provides Many Parallel Operations per Cycle
- 2K-Byte Instruction Cache and 8K-Byte Data RAM per PP
- Transfer Controller (TC)
- 64-Bit Data Transfers
- Up to 400 Megabytes per Second (MBps) Transfer Rate
- 32-Bit Addressing
- Direct DRAM/VRAM Interface With Dynamic Bus Sizing
- Intelligent Queuing and Cycle Prioritization
- Video Controller (VC)
- Provides Video Timing and Video Random-Access Memory (VRAM) Control
- Dual-Frame Timers for Two Simultaneous Image-Capture and/or Display Systems
- Big- or Little-Endian Operation
- 50K-Byte On-Chip RAM
- 4G-Byte Address Space
- 20-ns Cycle Time
- 3.3-V Operation
- IEEE Standard 1149.1
Test Access Port (JTAG) - Operating Temperature Range
–55°C to 125°C - M-Temperature
–40°C to 85°C - A-Temperature
IEEE Standard 1149.1–1990, IEEE Standard Test Access Port and Boundary-Scan Architecture
The SMJ320C80 is a single-chip, MIMD parallel processor capable of performing over two billion operations per second. It consists of a 32-bit RISC master processor with a 100-MFLOPS (million floating-point operations per second) IEEE floating-point unit, four 32-bit parallel processing digital signal processors (DSPs), a transfer controller with up to 400-MBps off-chip transfer rate, and a video controller. All the processors are coupled tightly through an on-chip crossbar that provides shared access to on-chip RAM. This performance and programmability make the ?C80 ideally suited for video, imaging, and high-speed telecommunications applications.
