There are a number of DxDesigner translators that are accessible from a number of different sources as described in the following topics： ? CADStar Schematic and Library Translator ? OrCAD Schematic and Library Translator ? PADS Logic Schematic and Library Translator ? P-CAD Schematic and Library Translator ? Altium （Protel） Schematic and Library Translator ? EDIF Translation Tools （EDIF Translators - Overview） ? Agilent Environments Translator ? Design Architect Schematic Translator ? Design Capture Schematic Translators Note Prerequisite： Before you execute any of the translators from （DxDesigner） 》 File 》 Export （except Design Architect and Design Capture）， you should first create a new DxDesigner project as described in Project Creation in the DxDesigner User’s Guide. In addition to the schematic translators above that are used to translate a design between DxDesigner and another design tool， it is possible to output a netlist of a DxDesigner design for use by a simulator. A netlist is an ASCII file that identifies all the nets， busses， properties， and signals that are in your design. The design may be a single schematic or a complex design hierarchy. The netlist is the required input for simulation. DxDesigner provides the following netlister：