集成的DSP和RISC內核設置新的性能上限

　　微控制器（MCU）解決了低端，數字信號處理（DSP）為核心的應用多年，硬件乘法累加（MAC）在數字信號控制器（DSC）單位，大大擴展了DSP的能力。不過，MCU集成的外設和存儲器已經遠遠低于水平的專用DSP為核心處理器，微處理器，DSP核心還整合了一次了。性能的差距正在縮小，但是，隨著多核MCU產品供應商如德克薩斯儀器（TI）和恩智浦半導體。讓我們探索面向DSP挑戰的嵌入式設計人員的最新選擇，但它們也面臨著系統覆蓋率和功耗問題，這些問題通常會導致基于MCU的方法。

　　強大的DSP為中心的能力，MCU可以追溯到十年在這一點上的第一個電池介紹。Microchip DSC的杜撰術語dsPIC30家庭結合16位PIC24單片機硬件乘法累加（MAC）引進能力和其他DSP為核心的功能，如桶式移位器。TI走近段不同，利用處理器技術的DSP核心遺產并將其融入在C2000系列的存儲器和外設的MCU架構。

　　Multi-core MCUs

　　The DSC architectures mentioned above are single-core designs whether based on an MCU or DSP legacy. The latest TI and NXP DSP-centric offerings， however， are true multi-core designs. The intent in each case is to dedicate a core to the tasks for which it is best suited.

　　TI‘s new Concerto family such as the XF28M35H52C1RFPT combines a C28x DSP-centric core， including a floating-point unit （FPU）， that is essentially evolved from the TMS320F283x Delfino MCU family with an ARM Cortex-M3 RISC core that the company has used in the StellarisMCU family. In reality， designers that utilize Concerto get two MCUs in one as depicted in the block diagram （Figure 1）。 Each core has its own dedicated set of memory and peripherals. There is also a block of shared resources that support power clock and clock distribution， and interprocessor communications， and implement basic analog peripherals.