資料介紹
MM54HC390/MM74HC390
Dual 4-Bit Decade Counter
MM54HC393/MM74HC393
Dual 4-Bit Binary Counter
General Description
These counter circuits contain independent ripple carry
counters and utilize advanced silicon-gate CMOS technology.
The MM54HC390/MM74HC390 incorporate dual decade
counters, each composed of a divide-by-two and a divide-
by-five counter. The divide-by-two and divide-by-five
counters can be cascaded to form dual decade, dual bi-quinary,
or various combinations up to a single divide-by-100
counter. The MM54HC393/MM74HC393 contain two 4-bit
ripple carry binary counters, which can be cascaded to create
a single divide-by-256 counter.
Each of the two 4-bit counters is incremented on the high to
low transition (negative edge) of the clock input, and each
has an independent clear input. When clear is set high all
four bits of each counter are set to a low level. This enables
count truncation and allows the implementation of divide-by-
N counter configurations.
Each of the counters outputs can drive 10 low power
Schottky TTL equivalent loads. These counters are functionally
as well as pin equivalent to the 54LS390/74LS390
and the 54LS393/74LS393, respectively. All inputs are protected
from damage due to static discharge by diodes to
VCC and ground.
Features
Y Typical operating frequency: 50 MHz
Y Typical propagation delay: 13 ns (Ck to QA)
Y Wide operating supply voltage range: 2±6V
Y Low input current: k1 mA
Y Low quiescent supply current: 80 mA maximum
(74HC Series)
Y Fanout of 10 LS-TTL loads
Dual 4-Bit Decade Counter
MM54HC393/MM74HC393
Dual 4-Bit Binary Counter
General Description
These counter circuits contain independent ripple carry
counters and utilize advanced silicon-gate CMOS technology.
The MM54HC390/MM74HC390 incorporate dual decade
counters, each composed of a divide-by-two and a divide-
by-five counter. The divide-by-two and divide-by-five
counters can be cascaded to form dual decade, dual bi-quinary,
or various combinations up to a single divide-by-100
counter. The MM54HC393/MM74HC393 contain two 4-bit
ripple carry binary counters, which can be cascaded to create
a single divide-by-256 counter.
Each of the two 4-bit counters is incremented on the high to
low transition (negative edge) of the clock input, and each
has an independent clear input. When clear is set high all
four bits of each counter are set to a low level. This enables
count truncation and allows the implementation of divide-by-
N counter configurations.
Each of the counters outputs can drive 10 low power
Schottky TTL equivalent loads. These counters are functionally
as well as pin equivalent to the 54LS390/74LS390
and the 54LS393/74LS393, respectively. All inputs are protected
from damage due to static discharge by diodes to
VCC and ground.
Features
Y Typical operating frequency: 50 MHz
Y Typical propagation delay: 13 ns (Ck to QA)
Y Wide operating supply voltage range: 2±6V
Y Low input current: k1 mA
Y Low quiescent supply current: 80 mA maximum
(74HC Series)
Y Fanout of 10 LS-TTL loads
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