資料介紹
The MCP1727 is a 1.5A Low Dropout (LDO) linear
regulator that provides high current and low output
voltages in a very small package. The MCP1727
comes in a fixed (or adjustable) output voltage version,
with an output voltage range of 0.8V to 5.0V. The 1.5A
output current capability, combined with the low output
voltage capability, make the MCP1727 a good choice
for new sub-1.8V output voltage LDO applications that
have high current demands.
The MCP1727 is stable using ceramic output
capacitors that inherently provide lower output noise
and reduce the size and cost of the entire regulator
solution. Only 1 μF of output capacitance is needed to
stabilize the LDO.
Using CMOS construction, the quiescent current
consumed by the MCP1727 is typically less than
120 μA over the entire input voltage range, making it
attractive for portable computing applications that
demand high output current. When shut down, the
quiescent current is reduced to less than 0.1 μA.
The scaled-down output voltage is internally monitored
and a power good (PWRGD) output is provided when
the output is within 92% of regulation (typical). An
external capacitor can be used on the CDELAY pin to
adjust the delay from 200 μs to 300 ms.
The overtemperature and short circuit current-limiting
provide additional protection for the LDO during system
fault conditions.
regulator that provides high current and low output
voltages in a very small package. The MCP1727
comes in a fixed (or adjustable) output voltage version,
with an output voltage range of 0.8V to 5.0V. The 1.5A
output current capability, combined with the low output
voltage capability, make the MCP1727 a good choice
for new sub-1.8V output voltage LDO applications that
have high current demands.
The MCP1727 is stable using ceramic output
capacitors that inherently provide lower output noise
and reduce the size and cost of the entire regulator
solution. Only 1 μF of output capacitance is needed to
stabilize the LDO.
Using CMOS construction, the quiescent current
consumed by the MCP1727 is typically less than
120 μA over the entire input voltage range, making it
attractive for portable computing applications that
demand high output current. When shut down, the
quiescent current is reduced to less than 0.1 μA.
The scaled-down output voltage is internally monitored
and a power good (PWRGD) output is provided when
the output is within 92% of regulation (typical). An
external capacitor can be used on the CDELAY pin to
adjust the delay from 200 μs to 300 ms.
The overtemperature and short circuit current-limiting
provide additional protection for the LDO during system
fault conditions.
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