32位/33M 從模式(target)PCI接口參考設計，Lattice提供。由于PCI時序較復雜，此設計僅能供參考

The evolution of digital systems over the past two decades has placed new requirements on system designers.
They now need to design interfaces that are both high performance and compatible with other vendors’ systems. At
the same, time they need to meet immense time-to-market demands. The compatibility issue has been resolved by
designing systems with bus interfaces that are standards in the industry such as ISA, EISA, VESA and Micro Channel.
As performance became an ever more important factor, a new interface standard called PCI (Peripheral Component
Interconnect) was developed to meet the new requirements of today’s digital computer systems. PCI’s top
features include a well-documented standard supported by a special interest group and the performance of a
33MHz, 32-bit version of the specification reaching 132Mbytes per second at its peak transfer rate. This document
is a reference design solution for a 33MHz, 32-bit PCI target for ispMACH? devices. It is designed to provide users
with a starting point for designing a PCI target into a Lattice CPLD.