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　The Verilog? Hardware Description Language （Verilog HDL） became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple， intuitive， and effective at multiple levels of abstraction in a standard textual format for a variety of design tools， including verification simulation， timing analysis， test analysis， and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice by an overwhelming number of IC designers. Verilog contains a rich set of built-in primitives， including logic gates， user-definable primitives， switches， and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels is essentially provided by the semantics of two data types： nets and variables. Continuous assignments， in which expressions of both variables and nets can continuously drive values onto nets， provide the basic structural construct. Procedural assignments， in which the results of calculations involving variable and net values can be stored into variables， provide the basic behavioral construct. A design consists of a set of modules， each of which has an I/O interface， and a description of its function， which can be structural， behavioral， or a mix. These modules are formed into a hierarchy and are interconnected with nets. The Verilog language is extensible via the Programming Language Interface （PLI） and the Verilog Procedural Interface （VPI） routines. The PLI/VPI is a collection of routines that allows foreign functions to access information contained in a Verilog HDL description of the design and facilitates dynamic interaction with simulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulation and CAD systems， customized debugging tasks， delay calculators， and annotators. The language that influenced Verilog HDL the most was HILO-2， which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of Defense. HILO-2 successfully combined the gate and register transfer levels of abstraction and supported verification simulation， timing analysis， fault simulation， and test generation. In 1990， Cadence Design Systems placed the Verilog HDL into the public domain and the independent Open Verilog International （OVI） was formed to manage and promote Verilog HDL. In 1992， the Board of Directors of OVI began an effort to establish Verilog HDL as an IEEE standard. In 1993， the first IEEE Working Group was formed and after 18 months of focused efforts Verilog became an IEEE standard as IEEE Std 1364-1995. After the standardization process was complete the 1364 Working Group started looking for feedback from 1364 users worldwide so the standard could be enhanced and modified accordingly. This led to a five year effort to get a much better Verilog standard in IEEE Std 1364-2001