D 類音頻功放芯片輸出級電路的設(shè)計(jì)
劉偉,鄒月嫻,黃令華
（北京大學(xué)深圳研究生院 集成微系統(tǒng)科學(xué)工程與應(yīng)用國家級重點(diǎn)實(shí)驗(yàn)室 深圳518055）
摘要： 在D 類功放中，輸出功率管有比較大的容性負(fù)載，會嚴(yán)重影響芯片的輸出效能，本文基于Winbond0.5μCMOS 工藝設(shè)計(jì)了一種適用于D 類音頻功放的驅(qū)動電路，在前置驅(qū)動級加入時鐘控制信號，實(shí)現(xiàn)邏輯控制功能；合理設(shè)置功率管輸出的死區(qū)時間，避免了功率管的同時導(dǎo)通，提升了電路的工作效率、改善了總諧波失真（THD）和毛刺電壓。
關(guān)鍵詞：D 類音頻功放；輸出級；功率管；橋接負(fù)載
Design output stage for ClassD audio amplifier chip
LIU-Wei, ZOU Yue-xian, HUANG Ling-hua
(Shenzhen Graduate School of Peking University, Key Laboratory of Integrated Microsystems, Guangdong
Shenzhen 518055, China)
Abstract: In ClassD audio power amplifier, there is a large parasitic capacitor with output power mosfets, which will seriously affect the performance of the chip. Based on the process of Winbond05u CMOS, this paper presents a driver circuit for the ClassD audio power amplifier. In the predriver stage, the clock signal is added to achieve the function of control logic. The proper deadtime is set to avoid the power mosfets(NMOS&PMOS) conduction at the same time, it will increase the efficiency of the circuit, with the improvement of the THD (Total Harmonic Distortion)and voltage spike.
Key: ClassD audio power amplifier；output level；power mosfets；BTL.