本文轉(zhuǎn)載自：VagueCheung的博客

Vivado2017.2 中BRAM版本為 Block Memory Generator Specific Features 8.3

BRAM IP核包括有5種類型：

Single-port RAM 單端口RAM

Simple Dual-port RAM 簡(jiǎn)單雙端口RAM（A寫數(shù)據(jù)B讀數(shù)據(jù)）

True Dual-port RAM 雙端口RAM

Single-por ROM 單端口ROM

Dual-port ROM 雙端口ROM

BRAM核支持兩種總線形式的輸入輸出：Native or AXI4

以下圖配置為例：Single-port RAM

Testbench 測(cè)試代碼如下：

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 2018/11/21 15:52:48

// Design Name:

// Module Name: test_bench_BRAM

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module test_bench_BRAM(

);

reg[15:0] mem1_re[0:15]; //輸入數(shù)據(jù)存儲(chǔ)器

integer i;

// blk_mem_gen_0 inputs

reg clka;

reg ena;

reg wea;

reg[3:0] addra;

reg[15:0] dina;

// blk_mem_gen_0 outputs

wire[15:0] douta;

blk_mem_gen_0 blk_mem_gen_m0

(

.clka(clka), //BRAM 輸入時(shí)鐘信號(hào)

.ena(ena), //BRAM 時(shí)鐘使能信號(hào)

.wea(wea), //寫使能信號(hào)

.addra(addra), //地址信號(hào)

.dina(dina), //數(shù)據(jù)輸入接口 寫入

.douta(douta) //數(shù)據(jù)輸出接口 讀出

);

always #5 clka = ~clka;

initial $readmemh("D:/fpga/fft1/stimulus1_24bit.dat",mem1_re); //數(shù)據(jù)是[1 2 3 4 5 6 7 8 9]

initial begin

clka = 0;

ena = 0;

wea = 0;

addra = 0;

dina = 0;

#150 ena = 1;

begin

for(i=0;i

#10 wea

addra

/*if(i == 0) begin

addra

end

else if (i == 1) begin

addra

end

else if(i == 2) begin

addra

end

else if(i == 3) begin

addra

end

else begin

wea

end*/

dina

if(i == 15) begin

dina

wea

end

$display("mem_a[%d] = %h", i, mem1_re[i]);

end

end

#40000 $finish;

end

endmodule

仿真結(jié)果如下：

配置為simple dual port ram

Testbench

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 2018/11/21 15:52:48

// Design Name:

// Module Name: test_bench_BRAM

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module test_bench_BRAM(

);

reg[15:0] mem1_re[0:15]; //輸入數(shù)據(jù)存儲(chǔ)器

integer i;

integer j;

// blk_mem_gen_0 inputs

reg clk;

reg ena;

reg enb;

reg wea;

reg[3:0] addra;

reg[3:0] addrb;

reg[15:0] dina;

// blk_mem_gen_0 outputs

wire[15:0] douta;

wire[15:0] doutb;

/*****單端口 網(wǎng)絡(luò)配置的IP核

blk_mem_gen_0 blk_mem_gen_m0

(

.clka(clka), //BRAM 輸入時(shí)鐘信號(hào)

.ena(ena), //BRAM 時(shí)鐘使能信號(hào)

.wea(wea), //寫使能信號(hào)

.addra(addra), //地址信號(hào)

.dina(dina), //數(shù)據(jù)輸入接口 寫入

.douta(douta)

);*******/

/**************簡(jiǎn)單雙端口RAM A進(jìn)B出**************/

blk_mem_gen_0 blk_mem_gen_m0

(

.clka(clk), //BRAM 輸入時(shí)鐘信號(hào)

.ena(ena), //BRAM 時(shí)鐘使能信號(hào)

.wea(wea), //寫使能信號(hào)

.addra(addra), //地址信號(hào)

.dina(dina), //數(shù)據(jù)輸入接口 寫入

.clkb(clk), //BRAM 輸入時(shí)鐘信號(hào)

.enb(enb), //BRAM 時(shí)鐘使能信號(hào)

.addrb(addrb), //地址信號(hào)

.doutb(doutb)

);

always #5 clk = ~clk;

initial $readmemh("D:/fpga/fft1/stimulus1_24bit.dat",mem1_re);

initial begin

clk = 0;

ena = 0;

enb = 0;

wea = 0;

addra = 0;

addrb = 0;

dina = 0;

#150 ena = 1;

begin

for(i=0;i

#10 wea

addra

dina

if(i == 15) begin

dina

wea

addra

end

$display("mem_a[%d] = %h", i, mem1_re[i]);

end

for(j=0;j

#10 addrb

enb

if( j == 15) begin

enb

addrb

end

end

end

#40000 $finish;

end

endmodule

測(cè)試仿真結(jié)果：