CPLD design has advanced significantly beyond that of fast
PAL design. Today's CPLDs must operate in systems that
include microprocessors, memories, I/O devices, buses,
multiple power supplies and multiple frequency clocks. The
actual logic design is frequently minor with respect to the
electrical issues that must be dealt with during debug.
Discovering electrical problems at debug is too late. The
printed circuit board has been built and may have to be significantly
changed to debug. The best approach is to avoid
the problem. By anticipating common problems, designs
can be substantially “bullet-proofed” before debug. This,
means planning for options at the outset is the best solution.
Like NASA space flights, a thorough, but practical
checklist is one aspect of planning for success. This application
note provides a framework for checklisting a design
early, to eliminate problems.