1.0 INTRODUCTION .............................................5
2.0 ARCHITECTURE AND IMPLEMENTATION ...5
2.1 16-Mbyte Memory Pages, CIS and Memory
Array Decoder Logic....................................5
2.2 Selection and Command Logic.....................7
2.3 Address Extension Registers .......................7
2.4 Lower 24 Address Line Buffers ....................8
2.5 Data Transceiver..........................................8
3.0 CARD INFORMATION STRUCTURE (CIS) ....8
4.0 GENERAL DESIGN TRADEOFF
CONSIDERATIONS .....................................10
5.0 GENERAL SYSTEM DESIGN
CONSIDERATIONS .....................................11
6.0 SUMMARY ....................................................14
APPENDIX A: Ordering Information .................15
FIGURES
Figure 1. > 64-Mbyte PC Card with 16-Mbyte
Memory Paging ..................................6