提出了H.264/AVC 硬件編碼器的一種3 級流水結構，以此來提高硬件加速電路的
處理能力和利用效率。鑒于H.264 編碼芯片驗證的復雜性,還提出了一種基于ADSP-BF537
的新型多媒體SoC 驗證平臺，并討論了如何利用BF537，對H.264 編碼芯片進行全面、高效的軟硬件協同驗證。
【關鍵字】H.264 編碼器；硬件加速器；ADSP-BF537；軟硬件協同驗證；SoC
【中圖分類號】TN919.81 【文獻標識碼】A
Design of H.264 Video Encoder Based on ASIC and Its ADSP
Verification
WANG Yi，LIN Zu-lun
( Department of Optoelectronic Information, UESTC, Chengdu Sichuan 610054 China)
【Abstract】To improving the process capabilities and utilized efficiency of the hardware
accelerator, 3 pipeline architecture for H.264 video encoder is presented. This paper also
introduces a novel multimedia SoC verification platform based on ADSP-BF537 since the
verification of H.264 encoder chips is so complexity, and finally, How to using BF537 for
software/hardware co-verifing the H.264 encoder chip completely and effectively is discussed.
【Key words】H.264 video encoder; Hardware accelerator; ADSP-BF537; Software/hardware
co-verification; SoC